1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6
7 / {
8 compatible = "socionext,sc2000a";
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "socionext,milbeaut-m10v-smp";
17 cpu@f00 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a7";
20 reg = <0xf00>;
21 };
22 cpu@f01 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a7";
25 reg = <0xf01>;
26 };
27 cpu@f02 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0xf02>;
31 };
32 cpu@f03 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0xf03>;
36 };
37 };
38
39 timer { /* The Generic Timer */
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13
42 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
43 <GIC_PPI 14
44 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
45 <GIC_PPI 11
46 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
47 <GIC_PPI 10
48 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
49 clock-frequency = <40000000>;
50 always-on;
51 };
52
53 soc {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58 interrupt-parent = <&gic>;
59
60 gic: interrupt-controller@1d000000 {
61 compatible = "arm,cortex-a7-gic";
62 interrupt-controller;
63 #interrupt-cells = <3>;
64 reg = <0x1d001000 0x1000>,
65 <0x1d002000 0x1000>; /* CPU I/f base and size */
66 };
67
68 clk: clock-ctrl@1d021000 {
69 compatible = "socionext,milbeaut-m10v-ccu";
70 #clock-cells = <1>;
71 reg = <0x1d021000 0x1000>;
72 clocks = <&uclk40xi>;
73 };
74
75 timer@1e000050 { /* 32-bit Reload Timers */
76 compatible = "socionext,milbeaut-timer";
77 reg = <0x1e000050 0x20>;
78 interrupts = <0 91 4>;
79 clocks = <&clk 4>;
80 };
81
82 uart1: serial@1e700010 { /* PE4, PE5 */
83 /* Enable this as ttyUSI0 */
84 compatible = "socionext,milbeaut-usio-uart";
85 reg = <0x1e700010 0x10>;
86 interrupts = <0 141 0x4>, <0 149 0x4>;
87 interrupt-names = "rx", "tx";
88 clocks = <&clk 2>;
89 };
90
91 };
92
93 sram@0 {
94 compatible = "mmio-sram";
95 reg = <0x0 0x10000>;
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges = <0 0x0 0x10000>;
99 smp-sram@f100 {
100 compatible = "socionext,milbeaut-smp-sram";
101 reg = <0xf100 0x20>;
102 };
103 };
104 };
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