1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 */
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 gp0_reserved: rproc@45000000 {
21 compatible = "shared-dma-pool";
22 reg = <0x45000000 0x00400000>;
23 no-map;
24 };
25
26 delta_reserved: rproc@44000000 {
27 compatible = "shared-dma-pool";
28 reg = <0x44000000 0x01000000>;
29 no-map;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
43
44 /* kHz uV */
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
48 500000 0>;
49
50 clocks = <&clk_m_a9>;
51 clock-names = "cpu";
52 clock-latency = <100000>;
53 cpu0-supply = <&pwm_regulator>;
54 st,syscfg = <&syscfg_core 0x8e0>;
55 #cooling-cells = <2>;
56 };
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <1>;
61
62 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
63 cpu-release-addr = <0x94100A4>;
64
65 /* kHz uV */
66 operating-points = <1500000 0
67 1200000 0
68 800000 0
69 500000 0>;
70 #cooling-cells = <2>;
71 };
72 };
73
74 intc: interrupt-controller@8761000 {
75 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
77 interrupt-controller;
78 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
79 };
80
81 scu@8760000 {
82 compatible = "arm,cortex-a9-scu";
83 reg = <0x08760000 0x1000>;
84 };
85
86 timer@8760200 {
87 interrupt-parent = <&intc>;
88 compatible = "arm,cortex-a9-global-timer";
89 reg = <0x08760200 0x100>;
90 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&arm_periph_clk>;
92 };
93
94 l2: cache-controller@8762000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x08762000 0x1000>;
97 arm,data-latency = <3 3 3>;
98 arm,tag-latency = <2 2 2>;
99 cache-unified;
100 cache-level = <2>;
101 };
102
103 arm-pmu {
104 interrupt-parent = <&intc>;
105 compatible = "arm,cortex-a9-pmu";
106 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
107 };
108
109 pwm_regulator: pwm-regulator {
110 compatible = "pwm-regulator";
111 pwms = <&pwm1 3 8448>;
112 regulator-name = "CPU_1V0_AVS";
113 regulator-min-microvolt = <784000>;
114 regulator-max-microvolt = <1299000>;
115 regulator-always-on;
116 status = "okay";
117 };
118
119 restart: restart-controller {
120 compatible = "st,stih407-restart";
121 st,syscfg = <&syscfg_sbc_reg>;
122 status = "okay";
123 };
124
125 powerdown: powerdown-controller {
126 compatible = "st,stih407-powerdown";
127 #reset-cells = <1>;
128 };
129
130 softreset: softreset-controller {
131 compatible = "st,stih407-softreset";
132 #reset-cells = <1>;
133 };
134
135 picophyreset: picophyreset-controller {
136 compatible = "st,stih407-picophyreset";
137 #reset-cells = <1>;
138 };
139
140 irq-syscfg {
141 compatible = "st,stih407-irq-syscfg";
142 st,syscfg = <&syscfg_core>;
143 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
144 <ST_IRQ_SYSCFG_PMU_1>;
145 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
146 <ST_IRQ_SYSCFG_DISABLED>;
147 };
148
149 usb2_picophy0: phy1 {
150 compatible = "st,stih407-usb2-phy";
151 #phy-cells = <0>;
152 st,syscfg = <&syscfg_core 0x100 0xf4>;
153 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
154 <&picophyreset STIH407_PICOPHY2_RESET>;
155 reset-names = "global", "port";
156 };
157
158 miphy28lp_phy: miphy28lp {
159 compatible = "st,miphy28lp-phy";
160 st,syscfg = <&syscfg_core>;
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 phy_port0: port@9b22000 {
166 reg = <0x9b22000 0xff>,
167 <0x9b09000 0xff>,
168 <0x9b04000 0xff>;
169 reg-names = "sata-up",
170 "pcie-up",
171 "pipew";
172
173 st,syscfg = <0x114 0x818 0xe0 0xec>;
174 #phy-cells = <1>;
175
176 reset-names = "miphy-sw-rst";
177 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
178 };
179
180 phy_port1: port@9b2a000 {
181 reg = <0x9b2a000 0xff>,
182 <0x9b19000 0xff>,
183 <0x9b14000 0xff>;
184 reg-names = "sata-up",
185 "pcie-up",
186 "pipew";
187
188 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
189
190 #phy-cells = <1>;
191
192 reset-names = "miphy-sw-rst";
193 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
194 };
195
196 phy_port2: port@8f95000 {
197 reg = <0x8f95000 0xff>,
198 <0x8f90000 0xff>;
199 reg-names = "pipew",
200 "usb3-up";
201
202 st,syscfg = <0x11c 0x820>;
203
204 #phy-cells = <1>;
205
206 reset-names = "miphy-sw-rst";
207 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
208 };
209 };
210
211 st231_gp0: st231-gp0 {
212 compatible = "st,st231-rproc";
213 memory-region = <&gp0_reserved>;
214 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
215 reset-names = "sw_reset";
216 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
217 clock-frequency = <600000000>;
218 st,syscfg = <&syscfg_core 0x22c>;
219 #mbox-cells = <1>;
220 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
221 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
222 };
223
224 st231_delta: st231-delta {
225 compatible = "st,st231-rproc";
226 memory-region = <&delta_reserved>;
227 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
228 reset-names = "sw_reset";
229 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
230 clock-frequency = <600000000>;
231 st,syscfg = <&syscfg_core 0x224>;
232 #mbox-cells = <1>;
233 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
234 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
235 };
236
237 delta0 {
238 compatible = "st,st-delta";
239 clock-names = "delta",
240 "delta-st231",
241 "delta-flash-promip";
242 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
243 <&clk_s_c0_flexgen CLK_ST231_DMU>,
244 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
245 };
246
247 soc {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 interrupt-parent = <&intc>;
251 ranges;
252 compatible = "simple-bus";
253
254 syscfg_sbc: sbc-syscfg@9620000 {
255 compatible = "st,stih407-sbc-syscfg", "syscon";
256 reg = <0x9620000 0x1000>;
257 };
258
259 syscfg_front: front-syscfg@9280000 {
260 compatible = "st,stih407-front-syscfg", "syscon";
261 reg = <0x9280000 0x1000>;
262 };
263
264 syscfg_rear: rear-syscfg@9290000 {
265 compatible = "st,stih407-rear-syscfg", "syscon";
266 reg = <0x9290000 0x1000>;
267 };
268
269 syscfg_flash: flash-syscfg@92a0000 {
270 compatible = "st,stih407-flash-syscfg", "syscon";
271 reg = <0x92a0000 0x1000>;
272 };
273
274 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
275 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
276 reg = <0x9600000 0x1000>;
277 };
278
279 syscfg_core: core-syscfg@92b0000 {
280 compatible = "st,stih407-core-syscfg", "syscon";
281 reg = <0x92b0000 0x1000>;
282
283 sti_sasg_codec: sti-sasg-codec {
284 compatible = "st,stih407-sas-codec";
285 #sound-dai-cells = <1>;
286 status = "disabled";
287 st,syscfg = <&syscfg_core>;
288 };
289 };
290
291 syscfg_lpm: lpm-syscfg@94b5100 {
292 compatible = "st,stih407-lpm-syscfg", "syscon";
293 reg = <0x94b5100 0x1000>;
294 };
295
296 /* Display */
297 vtg_main: sti-vtg-main@8d02800 {
298 compatible = "st,vtg";
299 reg = <0x8d02800 0x200>;
300 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
301 };
302
303 vtg_aux: sti-vtg-aux@8d00200 {
304 compatible = "st,vtg";
305 reg = <0x8d00200 0x100>;
306 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
307 };
308
309 serial@9830000 {
310 compatible = "st,asc";
311 reg = <0x9830000 0x2c>;
312 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
314 /* Pinctrl moved out to a per-board configuration */
315
316 status = "disabled";
317 };
318
319 serial@9831000 {
320 compatible = "st,asc";
321 reg = <0x9831000 0x2c>;
322 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_serial1>;
325 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
326
327 status = "disabled";
328 };
329
330 serial@9832000 {
331 compatible = "st,asc";
332 reg = <0x9832000 0x2c>;
333 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_serial2>;
336 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
337
338 status = "disabled";
339 };
340
341 /* SBC_ASC0 - UART10 */
342 sbc_serial0: serial@9530000 {
343 compatible = "st,asc";
344 reg = <0x9530000 0x2c>;
345 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_sbc_serial0>;
348 clocks = <&clk_sysin>;
349
350 status = "disabled";
351 };
352
353 serial@9531000 {
354 compatible = "st,asc";
355 reg = <0x9531000 0x2c>;
356 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_sbc_serial1>;
359 clocks = <&clk_sysin>;
360
361 status = "disabled";
362 };
363
364 i2c@9840000 {
365 compatible = "st,comms-ssc4-i2c";
366 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
367 reg = <0x9840000 0x110>;
368 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
369 clock-names = "ssc";
370 clock-frequency = <400000>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_i2c0_default>;
373 #address-cells = <1>;
374 #size-cells = <0>;
375
376 status = "disabled";
377 };
378
379 i2c@9841000 {
380 compatible = "st,comms-ssc4-i2c";
381 reg = <0x9841000 0x110>;
382 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
384 clock-names = "ssc";
385 clock-frequency = <400000>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_i2c1_default>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390
391 status = "disabled";
392 };
393
394 i2c@9842000 {
395 compatible = "st,comms-ssc4-i2c";
396 reg = <0x9842000 0x110>;
397 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
399 clock-names = "ssc";
400 clock-frequency = <400000>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_i2c2_default>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405
406 status = "disabled";
407 };
408
409 i2c@9843000 {
410 compatible = "st,comms-ssc4-i2c";
411 reg = <0x9843000 0x110>;
412 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
414 clock-names = "ssc";
415 clock-frequency = <400000>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_i2c3_default>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420
421 status = "disabled";
422 };
423
424 i2c@9844000 {
425 compatible = "st,comms-ssc4-i2c";
426 reg = <0x9844000 0x110>;
427 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
429 clock-names = "ssc";
430 clock-frequency = <400000>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_i2c4_default>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435
436 status = "disabled";
437 };
438
439 i2c@9845000 {
440 compatible = "st,comms-ssc4-i2c";
441 reg = <0x9845000 0x110>;
442 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
444 clock-names = "ssc";
445 clock-frequency = <400000>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_i2c5_default>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450
451 status = "disabled";
452 };
453
454
455 /* SSCs on SBC */
456 i2c@9540000 {
457 compatible = "st,comms-ssc4-i2c";
458 reg = <0x9540000 0x110>;
459 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk_sysin>;
461 clock-names = "ssc";
462 clock-frequency = <400000>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_i2c10_default>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467
468 status = "disabled";
469 };
470
471 i2c@9541000 {
472 compatible = "st,comms-ssc4-i2c";
473 reg = <0x9541000 0x110>;
474 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk_sysin>;
476 clock-names = "ssc";
477 clock-frequency = <400000>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_i2c11_default>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482
483 status = "disabled";
484 };
485
486 spi@9840000 {
487 compatible = "st,comms-ssc4-spi";
488 reg = <0x9840000 0x110>;
489 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
491 clock-names = "ssc";
492 pinctrl-0 = <&pinctrl_spi0_default>;
493 pinctrl-names = "default";
494 #address-cells = <1>;
495 #size-cells = <0>;
496
497 status = "disabled";
498 };
499
500 spi@9841000 {
501 compatible = "st,comms-ssc4-spi";
502 reg = <0x9841000 0x110>;
503 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
505 clock-names = "ssc";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_spi1_default>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 status = "disabled";
512 };
513
514 spi@9842000 {
515 compatible = "st,comms-ssc4-spi";
516 reg = <0x9842000 0x110>;
517 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
519 clock-names = "ssc";
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_spi2_default>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 status = "disabled";
526 };
527
528 spi@9843000 {
529 compatible = "st,comms-ssc4-spi";
530 reg = <0x9843000 0x110>;
531 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
533 clock-names = "ssc";
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_spi3_default>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 status = "disabled";
540 };
541
542 spi@9844000 {
543 compatible = "st,comms-ssc4-spi";
544 reg = <0x9844000 0x110>;
545 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
547 clock-names = "ssc";
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_spi4_default>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552
553 status = "disabled";
554 };
555
556 /* SBC SSC */
557 spi@9540000 {
558 compatible = "st,comms-ssc4-spi";
559 reg = <0x9540000 0x110>;
560 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clk_sysin>;
562 clock-names = "ssc";
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_spi10_default>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567
568 status = "disabled";
569 };
570
571 spi@9541000 {
572 compatible = "st,comms-ssc4-spi";
573 reg = <0x9541000 0x110>;
574 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clk_sysin>;
576 clock-names = "ssc";
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_spi11_default>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581
582 status = "disabled";
583 };
584
585 spi@9542000 {
586 compatible = "st,comms-ssc4-spi";
587 reg = <0x9542000 0x110>;
588 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&clk_sysin>;
590 clock-names = "ssc";
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_spi12_default>;
593 #address-cells = <1>;
594 #size-cells = <0>;
595
596 status = "disabled";
597 };
598
599 mmc0: sdhci@9060000 {
600 compatible = "st,sdhci-stih407", "st,sdhci";
601 status = "disabled";
602 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
603 reg-names = "mmc", "top-mmc-delay";
604 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-names = "mmcirq";
606 pinctrl-names = "default";
607 pinctrl-0 = <&pinctrl_mmc0>;
608 clock-names = "mmc", "icn";
609 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
610 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
611 bus-width = <8>;
612 };
613
614 mmc1: sdhci@9080000 {
615 compatible = "st,sdhci-stih407", "st,sdhci";
616 status = "disabled";
617 reg = <0x09080000 0x7ff>;
618 reg-names = "mmc";
619 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-names = "mmcirq";
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_sd1>;
623 clock-names = "mmc", "icn";
624 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
625 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
626 resets = <&softreset STIH407_MMC1_SOFTRESET>;
627 bus-width = <4>;
628 };
629
630 /* Watchdog and Real-Time Clock */
631 lpc@8787000 {
632 compatible = "st,stih407-lpc";
633 reg = <0x8787000 0x1000>;
634 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
635 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
636 timeout-sec = <120>;
637 st,syscfg = <&syscfg_core>;
638 st,lpc-mode = <ST_LPC_MODE_WDT>;
639 };
640
641 lpc@8788000 {
642 compatible = "st,stih407-lpc";
643 reg = <0x8788000 0x1000>;
644 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
645 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
646 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
647 };
648
649 spifsm: spifsm@9022000 {
650 compatible = "st,spi-fsm";
651 reg = <0x9022000 0x1000>;
652 reg-names = "spi-fsm";
653 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
654 clock-names = "emi_clk";
655 pinctrl-names = "default";
656 pinctrl-0 = <&pinctrl_fsm>;
657 st,syscfg = <&syscfg_core>;
658 st,boot-device-reg = <0x8c4>;
659 st,boot-device-spi = <0x68>;
660
661 status = "disabled";
662 };
663
664 sata0: sata@9b20000 {
665 compatible = "st,ahci";
666 reg = <0x9b20000 0x1000>;
667
668 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
669 interrupt-names = "hostc";
670
671 phys = <&phy_port0 PHY_TYPE_SATA>;
672 phy-names = "ahci_phy";
673
674 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
675 <&softreset STIH407_SATA0_SOFTRESET>,
676 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
677 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
678
679 clock-names = "ahci_clk";
680 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
681
682 ports-implemented = <0x1>;
683
684 status = "disabled";
685 };
686
687 sata1: sata@9b28000 {
688 compatible = "st,ahci";
689 reg = <0x9b28000 0x1000>;
690
691 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "hostc";
693
694 phys = <&phy_port1 PHY_TYPE_SATA>;
695 phy-names = "ahci_phy";
696
697 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
698 <&softreset STIH407_SATA1_SOFTRESET>,
699 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
700 reset-names = "pwr-dwn",
701 "sw-rst",
702 "pwr-rst";
703
704 clock-names = "ahci_clk";
705 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
706
707 ports-implemented = <0x1>;
708
709 status = "disabled";
710 };
711
712
713 st_dwc3: dwc3@8f94000 {
714 compatible = "st,stih407-dwc3";
715 reg = <0x08f94000 0x1000>, <0x110 0x4>;
716 reg-names = "reg-glue", "syscfg-reg";
717 st,syscfg = <&syscfg_core>;
718 resets = <&powerdown STIH407_USB3_POWERDOWN>,
719 <&softreset STIH407_MIPHY2_SOFTRESET>;
720 reset-names = "powerdown", "softreset";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_usb3>;
725 ranges;
726
727 status = "disabled";
728
729 dwc3: usb@9900000 {
730 compatible = "snps,dwc3";
731 reg = <0x09900000 0x100000>;
732 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
733 dr_mode = "host";
734 phy-names = "usb2-phy", "usb3-phy";
735 phys = <&usb2_picophy0>,
736 <&phy_port2 PHY_TYPE_USB3>;
737 snps,dis_u3_susphy_quirk;
738 };
739 };
740
741 /* COMMS PWM Module */
742 pwm0: pwm@9810000 {
743 compatible = "st,sti-pwm";
744 #pwm-cells = <2>;
745 reg = <0x9810000 0x68>;
746 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
749 clock-names = "pwm";
750 clocks = <&clk_sysin>;
751 st,pwm-num-chan = <1>;
752
753 status = "disabled";
754 };
755
756 /* SBC PWM Module */
757 pwm1: pwm@9510000 {
758 compatible = "st,sti-pwm";
759 #pwm-cells = <2>;
760 reg = <0x9510000 0x68>;
761 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_pwm1_chan0_default
764 &pinctrl_pwm1_chan1_default
765 &pinctrl_pwm1_chan2_default
766 &pinctrl_pwm1_chan3_default>;
767 clock-names = "pwm";
768 clocks = <&clk_sysin>;
769 st,pwm-num-chan = <4>;
770
771 status = "disabled";
772 };
773
774 rng10: rng@8a89000 {
775 compatible = "st,rng";
776 reg = <0x08a89000 0x1000>;
777 clocks = <&clk_sysin>;
778 status = "okay";
779 };
780
781 rng11: rng@8a8a000 {
782 compatible = "st,rng";
783 reg = <0x08a8a000 0x1000>;
784 clocks = <&clk_sysin>;
785 status = "okay";
786 };
787
788 ethernet0: dwmac@9630000 {
789 device_type = "network";
790 status = "disabled";
791 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
792 reg = <0x9630000 0x8000>, <0x80 0x4>;
793 reg-names = "stmmaceth", "sti-ethconf";
794
795 st,syscon = <&syscfg_sbc_reg 0x80>;
796 st,gmac_en;
797 resets = <&softreset STIH407_ETH1_SOFTRESET>;
798 reset-names = "stmmaceth";
799
800 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
802 interrupt-names = "macirq", "eth_wake_irq";
803
804 /* DMA Bus Mode */
805 snps,pbl = <8>;
806
807 pinctrl-names = "default";
808 pinctrl-0 = <&pinctrl_rgmii1>;
809
810 clock-names = "stmmaceth", "sti-ethclk";
811 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
812 <&clk_s_c0_flexgen CLK_ETH_PHY>;
813 };
814
815 mailbox0: mailbox@8f00000 {
816 compatible = "st,stih407-mailbox";
817 reg = <0x8f00000 0x1000>;
818 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
819 #mbox-cells = <2>;
820 mbox-name = "a9";
821 status = "okay";
822 };
823
824 mailbox1: mailbox@8f01000 {
825 compatible = "st,stih407-mailbox";
826 reg = <0x8f01000 0x1000>;
827 #mbox-cells = <2>;
828 mbox-name = "st231_gp_1";
829 status = "okay";
830 };
831
832 mailbox2: mailbox@8f02000 {
833 compatible = "st,stih407-mailbox";
834 reg = <0x8f02000 0x1000>;
835 #mbox-cells = <2>;
836 mbox-name = "st231_gp_0";
837 status = "okay";
838 };
839
840 mailbox3: mailbox@8f03000 {
841 compatible = "st,stih407-mailbox";
842 reg = <0x8f03000 0x1000>;
843 #mbox-cells = <2>;
844 mbox-name = "st231_audio_video";
845 status = "okay";
846 };
847
848 /* fdma audio */
849 fdma0: dma-controller@8e20000 {
850 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
851 reg = <0x8e20000 0x8000>,
852 <0x8e30000 0x3000>,
853 <0x8e37000 0x1000>,
854 <0x8e38000 0x8000>;
855 reg-names = "slimcore", "dmem", "peripherals", "imem";
856 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
857 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
858 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
859 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
860 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
861 dma-channels = <16>;
862 #dma-cells = <3>;
863 };
864
865 /* fdma app */
866 fdma1: dma-controller@8e40000 {
867 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
868 reg = <0x8e40000 0x8000>,
869 <0x8e50000 0x3000>,
870 <0x8e57000 0x1000>,
871 <0x8e58000 0x8000>;
872 reg-names = "slimcore", "dmem", "peripherals", "imem";
873 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
874 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
875 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
876 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
877
878 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
879 dma-channels = <16>;
880 #dma-cells = <3>;
881
882 status = "disabled";
883 };
884
885 /* fdma free running */
886 fdma2: dma-controller@8e60000 {
887 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
888 reg = <0x8e60000 0x8000>,
889 <0x8e70000 0x3000>,
890 <0x8e77000 0x1000>,
891 <0x8e78000 0x8000>;
892 reg-names = "slimcore", "dmem", "peripherals", "imem";
893 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
894 dma-channels = <16>;
895 #dma-cells = <3>;
896 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
897 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
898 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
899 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
900
901 status = "disabled";
902 };
903
904 sti_uni_player0: sti-uni-player@8d80000 {
905 compatible = "st,stih407-uni-player-hdmi";
906 #sound-dai-cells = <0>;
907 st,syscfg = <&syscfg_core>;
908 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
909 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
910 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
911 assigned-clock-rates = <50000000>;
912 reg = <0x8d80000 0x158>;
913 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
914 dmas = <&fdma0 2 0 1>;
915 dma-names = "tx";
916
917 status = "disabled";
918 };
919
920 sti_uni_player1: sti-uni-player@8d81000 {
921 compatible = "st,stih407-uni-player-pcm-out";
922 #sound-dai-cells = <0>;
923 st,syscfg = <&syscfg_core>;
924 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
925 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
926 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
927 assigned-clock-rates = <50000000>;
928 reg = <0x8d81000 0x158>;
929 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
930 dmas = <&fdma0 3 0 1>;
931 dma-names = "tx";
932
933 status = "disabled";
934 };
935
936 sti_uni_player2: sti-uni-player@8d82000 {
937 compatible = "st,stih407-uni-player-dac";
938 #sound-dai-cells = <0>;
939 st,syscfg = <&syscfg_core>;
940 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
941 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
942 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
943 assigned-clock-rates = <50000000>;
944 reg = <0x8d82000 0x158>;
945 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
946 dmas = <&fdma0 4 0 1>;
947 dma-names = "tx";
948
949 status = "disabled";
950 };
951
952 sti_uni_player3: sti-uni-player@8d85000 {
953 compatible = "st,stih407-uni-player-spdif";
954 #sound-dai-cells = <0>;
955 st,syscfg = <&syscfg_core>;
956 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
957 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
958 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
959 assigned-clock-rates = <50000000>;
960 reg = <0x8d85000 0x158>;
961 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
962 dmas = <&fdma0 7 0 1>;
963 dma-names = "tx";
964
965 status = "disabled";
966 };
967
968 sti_uni_reader0: sti-uni-reader@8d83000 {
969 compatible = "st,stih407-uni-reader-pcm_in";
970 #sound-dai-cells = <0>;
971 st,syscfg = <&syscfg_core>;
972 reg = <0x8d83000 0x158>;
973 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
974 dmas = <&fdma0 5 0 1>;
975 dma-names = "rx";
976
977 status = "disabled";
978 };
979
980 sti_uni_reader1: sti-uni-reader@8d84000 {
981 compatible = "st,stih407-uni-reader-hdmi";
982 #sound-dai-cells = <0>;
983 st,syscfg = <&syscfg_core>;
984 reg = <0x8d84000 0x158>;
985 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
986 dmas = <&fdma0 6 0 1>;
987 dma-names = "rx";
988
989 status = "disabled";
990 };
991 };
992 };
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