1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) Protonic Holland
4 * Author: David Jander <david@protonic.nl>
5 */
6 /dts-v1/;
7
8 #include "stm32mp151a-prtt1l.dtsi"
9
10 / {
11 model = "Protonic PRTT1C";
12 compatible = "prt,prtt1c", "st,stm32mp151";
13
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
18 };
19
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <25000000>;
24 };
25
26 pse_t1l1: ethernet-pse-1 {
27 compatible = "podl-pse-regulator";
28 pse-supply = <®_t1l1>;
29 #pse-cells = <0>;
30 };
31
32 pse_t1l2: ethernet-pse-2 {
33 compatible = "podl-pse-regulator";
34 pse-supply = <®_t1l2>;
35 #pse-cells = <0>;
36 };
37
38 mdio0: mdio {
39 compatible = "virtual,mdio-gpio";
40 #address-cells = <1>;
41 #size-cells = <0>;
42 gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
43 &gpioa 2 GPIO_ACTIVE_HIGH>;
44
45 };
46
47 reg_t1l1: regulator-pse-t1l1 {
48 compatible = "regulator-fixed";
49 regulator-name = "pse-t1l1";
50 regulator-min-microvolt = <12000000>;
51 regulator-max-microvolt = <12000000>;
52 gpio = <&gpiog 13 GPIO_ACTIVE_HIGH>;
53 enable-active-high;
54 };
55
56 reg_t1l2: regulator-pse-t1l2 {
57 compatible = "regulator-fixed";
58 regulator-name = "pse-t1l2";
59 regulator-min-microvolt = <12000000>;
60 regulator-max-microvolt = <12000000>;
61 gpio = <&gpiog 14 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 };
64
65 wifi_pwrseq: wifi-pwrseq {
66 compatible = "mmc-pwrseq-simple";
67 reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
68 };
69 };
70
71 ðernet0 {
72 fixed-link {
73 speed = <100>;
74 full-duplex;
75 };
76 };
77
78 &gpioa {
79 gpio-line-names =
80 "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
81 "", "", "", "", "", "", "", "SPI1_nSS";
82 };
83
84 &gpiod {
85 gpio-line-names =
86 "", "", "", "", "", "", "", "",
87 "WFM_RESET", "", "", "", "", "", "", "";
88 };
89
90 &gpioe {
91 gpio-line-names =
92 "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
93 "", "", "", "", "WFM_nIRQ", "", "", "";
94 };
95
96 &gpiog {
97 gpio-line-names =
98 "", "", "", "", "", "", "", "PHY3_nINT",
99 "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
100 "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
101 };
102
103 &mdio0 {
104 /* All this DP83TD510E PHYs can't be probed before switch@0 is
105 * probed so we need to use compatible with PHYid
106 */
107 /* TI DP83TD510E */
108 t1l0_phy: ethernet-phy@6 {
109 compatible = "ethernet-phy-id2000.0181";
110 reg = <6>;
111 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
112 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
113 reset-assert-us = <10>;
114 reset-deassert-us = <35>;
115 };
116
117 /* TI DP83TD510E */
118 t1l1_phy: ethernet-phy@7 {
119 compatible = "ethernet-phy-id2000.0181";
120 reg = <7>;
121 interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
122 reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
123 reset-assert-us = <10>;
124 reset-deassert-us = <35>;
125 pses = <&pse_t1l1>;
126 };
127
128 /* TI DP83TD510E */
129 t1l2_phy: ethernet-phy@10 {
130 compatible = "ethernet-phy-id2000.0181";
131 reg = <10>;
132 interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
133 reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
134 reset-assert-us = <10>;
135 reset-deassert-us = <35>;
136 pses = <&pse_t1l2>;
137 };
138
139 /* Micrel KSZ9031 */
140 rj45_phy: ethernet-phy@2 {
141 reg = <2>;
142 interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
143 reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
144 reset-assert-us = <10000>;
145 reset-deassert-us = <1000>;
146
147 clocks = <&clock_ksz9031>;
148 };
149 };
150
151 &qspi {
152 status = "disabled";
153 };
154
155 &sdmmc2 {
156 pinctrl-names = "default", "opendrain", "sleep";
157 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
158 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
159 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
160 non-removable;
161 no-sd;
162 no-sdio;
163 no-1-8-v;
164 st,neg-edge;
165 bus-width = <8>;
166 vmmc-supply = <®_3v3>;
167 vqmmc-supply = <®_3v3>;
168 status = "okay";
169 };
170
171 &{sdmmc2_b4_od_pins_a/pins1} {
172 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
173 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
174 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
175 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
176 };
177
178 &{sdmmc2_b4_pins_a/pins1} {
179 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
180 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
181 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
182 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
183 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
184 };
185
186 &{sdmmc2_b4_sleep_pins_a/pins} {
187 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
188 <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
189 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
190 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
191 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
192 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
193 };
194
195 &{sdmmc2_d47_pins_a/pins} {
196 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
197 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
198 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
199 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
200 };
201
202 &{sdmmc2_d47_sleep_pins_a/pins} {
203 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
204 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
205 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
206 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
207 };
208
209 &sdmmc3 {
210 pinctrl-names = "default", "opendrain", "sleep";
211 pinctrl-0 = <&sdmmc3_b4_pins_b>;
212 pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
213 pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
214 non-removable;
215 no-1-8-v;
216 st,neg-edge;
217 bus-width = <4>;
218 vmmc-supply = <®_3v3>;
219 vqmmc-supply = <®_3v3>;
220 mmc-pwrseq = <&wifi_pwrseq>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 status = "okay";
224
225 mmc@1 {
226 compatible = "prt,prtt1c-wfm200", "silabs,wf200";
227 reg = <1>;
228 };
229 };
230
231 &{sdmmc3_b4_od_pins_b/pins1} {
232 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
233 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
234 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
235 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
236 };
237
238 &{sdmmc3_b4_pins_b/pins1} {
239 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
240 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
241 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
242 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
243 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
244 };
245
246 &{sdmmc3_b4_sleep_pins_b/pins} {
247 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
248 <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
249 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
250 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
251 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
252 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
253 };
254
255 &spi1 {
256 pinctrl-0 = <&spi1_pins_b>;
257 pinctrl-names = "default";
258 cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
259 /delete-property/dmas;
260 /delete-property/dma-names;
261 status = "okay";
262
263 switch@0 {
264 compatible = "nxp,sja1105q";
265 reg = <0>;
266 spi-max-frequency = <4000000>;
267 spi-rx-delay-us = <1>;
268 spi-tx-delay-us = <1>;
269 spi-cpha;
270
271 reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
272
273 clocks = <&clock_sja1105>;
274
275 ports {
276 #address-cells = <1>;
277 #size-cells = <0>;
278
279 port@0 {
280 reg = <0>;
281 label = "t1l0";
282 phy-mode = "rmii";
283 phy-handle = <&t1l0_phy>;
284 };
285
286 port@1 {
287 reg = <1>;
288 label = "t1l1";
289 phy-mode = "rmii";
290 phy-handle = <&t1l1_phy>;
291 };
292
293 port@2 {
294 reg = <2>;
295 label = "t1l2";
296 phy-mode = "rmii";
297 phy-handle = <&t1l2_phy>;
298 };
299
300 port@3 {
301 reg = <3>;
302 label = "rj45";
303 phy-handle = <&rj45_phy>;
304 phy-mode = "rgmii-id";
305 };
306
307 port@4 {
308 reg = <4>;
309 label = "cpu";
310 ethernet = <ðernet0>;
311 phy-mode = "rmii";
312
313 fixed-link {
314 speed = <100>;
315 full-duplex;
316 };
317 };
318 };
319 };
320 };
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