1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * based on GPL'ed 2.6 kernel sources
8 * (c) Marvell International Ltd.
9 */
10
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13
14 / {
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
16 compatible = "marvell,berlin2cd", "marvell,berlin";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu: cpu@0 {
30 compatible = "arm,cortex-a9";
31 device_type = "cpu";
32 next-level-cache = <&l2>;
33 reg = <0>;
34
35 clocks = <&chip_clk CLKID_CPU>;
36 clock-latency = <100000>;
37 operating-points = <
38 /* kHz uV */
39 800000 1200000
40 600000 1200000
41 >;
42 };
43 };
44
45 pmu {
46 compatible = "arm,cortex-a9-pmu";
47 interrupt-parent = <&gic>;
48 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
49 };
50
51 refclk: oscillator {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <25000000>;
55 };
56
57 soc@f7000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 interrupt-parent = <&gic>;
62
63 ranges = <0 0xf7000000 0x1000000>;
64
65 sdhci0: mmc@ab0000 {
66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0000 0x200>;
68 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
69 clock-names = "io", "core";
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
71 status = "disabled";
72 };
73
74 l2: cache-controller@ac0000 {
75 compatible = "arm,pl310-cache";
76 reg = <0xac0000 0x1000>;
77 cache-unified;
78 cache-level = <2>;
79 };
80
81 snoop-control-unit@ad0000 {
82 compatible = "arm,cortex-a9-scu";
83 reg = <0xad0000 0x100>;
84 };
85
86 gic: interrupt-controller@ad1000 {
87 compatible = "arm,cortex-a9-gic";
88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
89 interrupt-controller;
90 #interrupt-cells = <3>;
91 };
92
93 global-timer@ad0200 {
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0xad0200 0x20>;
96 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
97 clocks = <&chip_clk CLKID_TWD>;
98 };
99
100 local-timer@ad0600 {
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0xad0600 0x20>;
103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
104 clocks = <&chip_clk CLKID_TWD>;
105 };
106
107 local-wdt@ad0620 {
108 compatible = "arm,cortex-a9-twd-wdt";
109 reg = <0xad0620 0x20>;
110 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
111 clocks = <&chip_clk CLKID_TWD>;
112 };
113
114 usb_phy0: usb-phy@b74000 {
115 compatible = "marvell,berlin2cd-usb-phy";
116 reg = <0xb74000 0x128>;
117 #phy-cells = <0>;
118 resets = <&chip_rst 0x178 23>;
119 status = "disabled";
120 };
121
122 usb_phy1: usb-phy@b78000 {
123 compatible = "marvell,berlin2cd-usb-phy";
124 reg = <0xb78000 0x128>;
125 #phy-cells = <0>;
126 resets = <&chip_rst 0x178 24>;
127 status = "disabled";
128 };
129
130 eth1: ethernet@b90000 {
131 compatible = "marvell,pxa168-eth";
132 reg = <0xb90000 0x10000>;
133 clocks = <&chip_clk CLKID_GETH1>;
134 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
135 /* set by bootloader */
136 local-mac-address = [00 00 00 00 00 00];
137 #address-cells = <1>;
138 #size-cells = <0>;
139 phy-connection-type = "mii";
140 phy-handle = <ðphy1>;
141 status = "disabled";
142
143 ethphy1: ethernet-phy@0 {
144 reg = <0>;
145 };
146 };
147
148 eth0: ethernet@e50000 {
149 compatible = "marvell,pxa168-eth";
150 reg = <0xe50000 0x10000>;
151 clocks = <&chip_clk CLKID_GETH0>;
152 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153 /* set by bootloader */
154 local-mac-address = [00 00 00 00 00 00];
155 #address-cells = <1>;
156 #size-cells = <0>;
157 phy-connection-type = "mii";
158 phy-handle = <ðphy0>;
159 status = "disabled";
160
161 ethphy0: ethernet-phy@0 {
162 reg = <0>;
163 };
164 };
165
166 apb@e80000 {
167 compatible = "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170
171 ranges = <0 0xe80000 0x10000>;
172 interrupt-parent = <&aic>;
173
174 gpio0: gpio@400 {
175 compatible = "snps,dw-apb-gpio";
176 reg = <0x0400 0x400>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 porta: gpio-port@0 {
181 compatible = "snps,dw-apb-gpio-port";
182 gpio-controller;
183 #gpio-cells = <2>;
184 ngpios = <8>;
185 reg = <0>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 interrupts = <0>;
189 };
190 };
191
192 gpio1: gpio@800 {
193 compatible = "snps,dw-apb-gpio";
194 reg = <0x0800 0x400>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 portb: gpio-port@1 {
199 compatible = "snps,dw-apb-gpio-port";
200 gpio-controller;
201 #gpio-cells = <2>;
202 ngpios = <8>;
203 reg = <0>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 interrupts = <1>;
207 };
208 };
209
210 gpio2: gpio@c00 {
211 compatible = "snps,dw-apb-gpio";
212 reg = <0x0c00 0x400>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215
216 portc: gpio-port@2 {
217 compatible = "snps,dw-apb-gpio-port";
218 gpio-controller;
219 #gpio-cells = <2>;
220 ngpios = <8>;
221 reg = <0>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
224 interrupts = <2>;
225 };
226 };
227
228 gpio3: gpio@1000 {
229 compatible = "snps,dw-apb-gpio";
230 reg = <0x1000 0x400>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233
234 portd: gpio-port@3 {
235 compatible = "snps,dw-apb-gpio-port";
236 gpio-controller;
237 #gpio-cells = <2>;
238 ngpios = <8>;
239 reg = <0>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
242 interrupts = <3>;
243 };
244 };
245
246 i2c0: i2c@1400 {
247 compatible = "snps,designware-i2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 reg = <0x1400 0x100>;
251 interrupts = <16>;
252 clocks = <&chip_clk CLKID_CFG>;
253 status = "disabled";
254 };
255
256 i2c1: i2c@1800 {
257 compatible = "snps,designware-i2c";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x1800 0x100>;
261 interrupts = <17>;
262 clocks = <&chip_clk CLKID_CFG>;
263 status = "disabled";
264 };
265
266 spi0: spi@1c00 {
267 compatible = "snps,dw-apb-ssi";
268 #address-cells = <1>;
269 #size-cells = <0>;
270 reg = <0x1c00 0x100>;
271 interrupts = <4>;
272 clocks = <&chip_clk CLKID_CFG>;
273 status = "disabled";
274 };
275
276 wdt4: watchdog@2000 {
277 compatible = "snps,dw-wdt";
278 reg = <0x2000 0x100>;
279 clocks = <&chip_clk CLKID_CFG>;
280 interrupts = <5>;
281 status = "disabled";
282 };
283
284 wdt5: watchdog@2400 {
285 compatible = "snps,dw-wdt";
286 reg = <0x2400 0x100>;
287 clocks = <&chip_clk CLKID_CFG>;
288 interrupts = <6>;
289 status = "disabled";
290 };
291
292 wdt6: watchdog@2800 {
293 compatible = "snps,dw-wdt";
294 reg = <0x2800 0x100>;
295 clocks = <&chip_clk CLKID_CFG>;
296 interrupts = <7>;
297 status = "disabled";
298 };
299
300 timer0: timer@2c00 {
301 compatible = "snps,dw-apb-timer";
302 reg = <0x2c00 0x14>;
303 interrupts = <8>;
304 clocks = <&chip_clk CLKID_CFG>;
305 clock-names = "timer";
306 status = "okay";
307 };
308
309 timer1: timer@2c14 {
310 compatible = "snps,dw-apb-timer";
311 reg = <0x2c14 0x14>;
312 interrupts = <9>;
313 clocks = <&chip_clk CLKID_CFG>;
314 clock-names = "timer";
315 status = "okay";
316 };
317
318 timer2: timer@2c28 {
319 compatible = "snps,dw-apb-timer";
320 reg = <0x2c28 0x14>;
321 interrupts = <10>;
322 clocks = <&chip_clk CLKID_CFG>;
323 clock-names = "timer";
324 status = "disabled";
325 };
326
327 timer3: timer@2c3c {
328 compatible = "snps,dw-apb-timer";
329 reg = <0x2c3c 0x14>;
330 interrupts = <11>;
331 clocks = <&chip_clk CLKID_CFG>;
332 clock-names = "timer";
333 status = "disabled";
334 };
335
336 timer4: timer@2c50 {
337 compatible = "snps,dw-apb-timer";
338 reg = <0x2c50 0x14>;
339 interrupts = <12>;
340 clocks = <&chip_clk CLKID_CFG>;
341 clock-names = "timer";
342 status = "disabled";
343 };
344
345 timer5: timer@2c64 {
346 compatible = "snps,dw-apb-timer";
347 reg = <0x2c64 0x14>;
348 interrupts = <13>;
349 clocks = <&chip_clk CLKID_CFG>;
350 clock-names = "timer";
351 status = "disabled";
352 };
353
354 timer6: timer@2c78 {
355 compatible = "snps,dw-apb-timer";
356 reg = <0x2c78 0x14>;
357 interrupts = <14>;
358 clocks = <&chip_clk CLKID_CFG>;
359 clock-names = "timer";
360 status = "disabled";
361 };
362
363 timer7: timer@2c8c {
364 compatible = "snps,dw-apb-timer";
365 reg = <0x2c8c 0x14>;
366 interrupts = <15>;
367 clocks = <&chip_clk CLKID_CFG>;
368 clock-names = "timer";
369 status = "disabled";
370 };
371
372 aic: interrupt-controller@3000 {
373 compatible = "snps,dw-apb-ictl";
374 reg = <0x3000 0xc00>;
375 interrupt-controller;
376 #interrupt-cells = <1>;
377 interrupt-parent = <&gic>;
378 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
379 };
380 };
381
382 chip: chip-control@ea0000 {
383 compatible = "simple-mfd", "syscon";
384 reg = <0xea0000 0x400>;
385
386 chip_clk: clock {
387 compatible = "marvell,berlin2-clk";
388 #clock-cells = <1>;
389 clocks = <&refclk>;
390 clock-names = "refclk";
391 };
392
393 soc_pinctrl: pin-controller {
394 compatible = "marvell,berlin2cd-soc-pinctrl";
395
396 uart0_pmux: uart0-pmux {
397 groups = "G6";
398 function = "uart0";
399 };
400 };
401
402 chip_rst: reset {
403 compatible = "marvell,berlin2-reset";
404 #reset-cells = <2>;
405 };
406 };
407
408 usb0: usb@ed0000 {
409 compatible = "chipidea,usb2";
410 reg = <0xed0000 0x200>;
411 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&chip_clk CLKID_USB0>;
413 phys = <&usb_phy0>;
414 phy-names = "usb-phy";
415 status = "disabled";
416 };
417
418 usb1: usb@ee0000 {
419 compatible = "chipidea,usb2";
420 reg = <0xee0000 0x200>;
421 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&chip_clk CLKID_USB1>;
423 phys = <&usb_phy1>;
424 phy-names = "usb-phy";
425 status = "disabled";
426 };
427
428 pwm: pwm@f20000 {
429 compatible = "marvell,berlin-pwm";
430 reg = <0xf20000 0x40>;
431 clocks = <&chip_clk CLKID_CFG>;
432 #pwm-cells = <3>;
433 };
434
435 apb@fc0000 {
436 compatible = "simple-bus";
437 #address-cells = <1>;
438 #size-cells = <1>;
439
440 ranges = <0 0xfc0000 0x10000>;
441 interrupt-parent = <&sic>;
442
443 wdt0: watchdog@1000 {
444 compatible = "snps,dw-wdt";
445 reg = <0x1000 0x100>;
446 clocks = <&refclk>;
447 interrupts = <0>;
448 };
449
450 wdt1: watchdog@2000 {
451 compatible = "snps,dw-wdt";
452 reg = <0x2000 0x100>;
453 clocks = <&refclk>;
454 interrupts = <1>;
455 status = "disabled";
456 };
457
458 wdt2: watchdog@3000 {
459 compatible = "snps,dw-wdt";
460 reg = <0x3000 0x100>;
461 clocks = <&refclk>;
462 interrupts = <2>;
463 status = "disabled";
464 };
465
466 sm_gpio1: gpio@5000 {
467 compatible = "snps,dw-apb-gpio";
468 reg = <0x5000 0x400>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471
472 portf: gpio-port@5 {
473 compatible = "snps,dw-apb-gpio-port";
474 gpio-controller;
475 #gpio-cells = <2>;
476 ngpios = <8>;
477 reg = <0>;
478 };
479 };
480
481 spi1: spi@6000 {
482 compatible = "snps,dw-apb-ssi";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <0x6000 0x100>;
486 clocks = <&refclk>;
487 interrupts = <5>;
488 status = "disabled";
489 };
490
491 i2c2: i2c@7000 {
492 compatible = "snps,designware-i2c";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 reg = <0x7000 0x100>;
496 interrupts = <6>;
497 clocks = <&refclk>;
498 status = "disabled";
499 };
500
501 i2c3: i2c@8000 {
502 compatible = "snps,designware-i2c";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 reg = <0x8000 0x100>;
506 interrupts = <7>;
507 clocks = <&refclk>;
508 status = "disabled";
509 };
510
511 sm_gpio0: gpio@c000 {
512 compatible = "snps,dw-apb-gpio";
513 reg = <0xc000 0x400>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516
517 porte: gpio-port@4 {
518 compatible = "snps,dw-apb-gpio-port";
519 gpio-controller;
520 #gpio-cells = <2>;
521 ngpios = <8>;
522 reg = <0>;
523 };
524 };
525
526 uart0: serial@9000 {
527 compatible = "snps,dw-apb-uart";
528 reg = <0x9000 0x100>;
529 reg-shift = <2>;
530 reg-io-width = <1>;
531 interrupts = <8>;
532 clocks = <&refclk>;
533 pinctrl-0 = <&uart0_pmux>;
534 pinctrl-names = "default";
535 status = "disabled";
536 };
537
538 uart1: serial@a000 {
539 compatible = "snps,dw-apb-uart";
540 reg = <0xa000 0x100>;
541 reg-shift = <2>;
542 reg-io-width = <1>;
543 interrupts = <9>;
544 clocks = <&refclk>;
545 status = "disabled";
546 };
547
548 uart2: serial@b000 {
549 compatible = "snps,dw-apb-uart";
550 reg = <0xb000 0x100>;
551 reg-shift = <2>;
552 reg-io-width = <1>;
553 interrupts = <10>;
554 clocks = <&refclk>;
555 status = "disabled";
556 };
557
558 sysctrl: system-controller@d000 {
559 compatible = "simple-mfd", "syscon";
560 reg = <0xd000 0x100>;
561
562 sys_pinctrl: pin-controller {
563 compatible = "marvell,berlin2cd-system-pinctrl";
564 };
565
566 adc: adc {
567 compatible = "marvell,berlin2-adc";
568 interrupts = <12>, <14>;
569 interrupt-names = "adc", "tsen";
570 };
571 };
572
573 sic: interrupt-controller@e000 {
574 compatible = "snps,dw-apb-ictl";
575 reg = <0xe000 0x400>;
576 interrupt-controller;
577 #interrupt-cells = <1>;
578 interrupt-parent = <&gic>;
579 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
580 };
581 };
582 };
583 };
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