1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 */
5 /dts-v1/;
6
7 #include "am33xx.dtsi"
8 #include <dt-bindings/interrupt-controller/irq.h>
9
10 / {
11 model = "TI AM335x EVM";
12 compatible = "ti,am335x-evm", "ti,am33xx";
13
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vdd1_reg>;
17 };
18 };
19
20 memory@80000000 {
21 device_type = "memory";
22 reg = <0x80000000 0x10000000>; /* 256 MB */
23 };
24
25 chosen {
26 stdout-path = &uart0;
27 };
28
29 vbat: fixedregulator0 {
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 regulator-boot-on;
35 };
36
37 lis3_reg: fixedregulator1 {
38 compatible = "regulator-fixed";
39 regulator-name = "lis3_reg";
40 regulator-boot-on;
41 };
42
43 wlan_en_reg: fixedregulator2 {
44 compatible = "regulator-fixed";
45 regulator-name = "wlan-en-regulator";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48
49 /* WLAN_EN GPIO for this board - Bank1, pin16 */
50 gpio = <&gpio1 16 0>;
51
52 /* WLAN card specific delay */
53 startup-delay-us = <70000>;
54 enable-active-high;
55 };
56
57 /* TPS79501 */
58 v1_8d_reg: fixedregulator-v1_8d {
59 compatible = "regulator-fixed";
60 regulator-name = "v1_8d";
61 vin-supply = <&vbat>;
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 };
65
66 /* TPS79501 */
67 v3_3d_reg: fixedregulator-v3_3d {
68 compatible = "regulator-fixed";
69 regulator-name = "v3_3d";
70 vin-supply = <&vbat>;
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 };
74
75 matrix_keypad: matrix_keypad0 {
76 compatible = "gpio-matrix-keypad";
77 debounce-delay-ms = <5>;
78 col-scan-delay-us = <2>;
79
80 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
81 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
82 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
83
84 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
85 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
86
87 linux,keymap = <0x0000008b /* MENU */
88 0x0100009e /* BACK */
89 0x02000069 /* LEFT */
90 0x0001006a /* RIGHT */
91 0x0101001c /* ENTER */
92 0x0201006c>; /* DOWN */
93 };
94
95 gpio_keys: volume-keys {
96 compatible = "gpio-keys";
97 autorepeat;
98
99 switch-9 {
100 label = "volume-up";
101 linux,code = <115>;
102 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
103 wakeup-source;
104 };
105
106 switch-10 {
107 label = "volume-down";
108 linux,code = <114>;
109 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
110 wakeup-source;
111 };
112 };
113
114 backlight: backlight {
115 compatible = "pwm-backlight";
116 pwms = <&ecap0 0 50000 0>;
117 brightness-levels = <0 51 53 56 62 75 101 152 255>;
118 default-brightness-level = <8>;
119 };
120
121 panel {
122 compatible = "tfc,s9700rtwv43tr-01b";
123
124 pinctrl-names = "default";
125 pinctrl-0 = <&lcd_pins_s0>;
126 backlight = <&backlight>;
127
128 port {
129 panel_0: endpoint {
130 remote-endpoint = <&lcdc_0>;
131 };
132 };
133 };
134
135 sound {
136 compatible = "simple-audio-card";
137 simple-audio-card,name = "AM335x-EVM";
138 simple-audio-card,widgets =
139 "Headphone", "Headphone Jack",
140 "Line", "Line In";
141 simple-audio-card,routing =
142 "Headphone Jack", "HPLOUT",
143 "Headphone Jack", "HPROUT",
144 "LINE1L", "Line In",
145 "LINE1R", "Line In";
146 simple-audio-card,format = "dsp_b";
147 simple-audio-card,bitclock-master = <&sound_master>;
148 simple-audio-card,frame-master = <&sound_master>;
149 simple-audio-card,bitclock-inversion;
150
151 simple-audio-card,cpu {
152 sound-dai = <&mcasp1>;
153 };
154
155 sound_master: simple-audio-card,codec {
156 sound-dai = <&tlv320aic3106>;
157 system-clock-frequency = <12000000>;
158 };
159 };
160 };
161
162 &am33xx_pinmux {
163 pinctrl-names = "default";
164 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
165
166 matrix_keypad_s0: matrix-keypad-s0-pins {
167 pinctrl-single,pins = <
168 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
169 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */
170 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */
171 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */
172 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */
173 >;
174 };
175
176 volume_keys_s0: volume-keys-s0-pins {
177 pinctrl-single,pins = <
178 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */
179 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */
180 >;
181 };
182
183 i2c0_pins: i2c0-pins {
184 pinctrl-single,pins = <
185 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */
186 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */
187 >;
188 };
189
190 i2c1_pins: i2c1-pins {
191 pinctrl-single,pins = <
192 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
193 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
194 >;
195 };
196
197 uart0_pins: uart0-pins {
198 pinctrl-single,pins = <
199 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
200 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
201 >;
202 };
203
204 uart1_pins: uart1-pins {
205 pinctrl-single,pins = <
206 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
207 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
208 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
209 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
210 >;
211 };
212
213 clkout2_pin: clkout2-pins {
214 pinctrl-single,pins = <
215 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
216 >;
217 };
218
219 nandflash_pins_s0: nandflash-s0-pins {
220 pinctrl-single,pins = <
221 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
222 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
223 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
224 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
225 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
226 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
227 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
228 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
229 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
230 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
231 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
232 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
233 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
234 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
235 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
236 >;
237 };
238
239 ecap0_pins: backlight-pins {
240 pinctrl-single,pins = <
241 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
242 >;
243 };
244
245 cpsw_default: cpsw-default-pins {
246 pinctrl-single,pins = <
247 /* Slave 1 */
248 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
249 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
250 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
251 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
252 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
253 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
254 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
255 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
256 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
257 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
258 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
259 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
260 >;
261 };
262
263 cpsw_sleep: cpsw-sleep-pins {
264 pinctrl-single,pins = <
265 /* Slave 1 reset value */
266 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
267 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
268 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
269 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
270 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
271 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
272 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
273 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
274 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
275 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
276 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
277 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
278 >;
279 };
280
281 davinci_mdio_default: davinci-mdio-default-pins {
282 pinctrl-single,pins = <
283 /* MDIO */
284 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
285 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
286 >;
287 };
288
289 davinci_mdio_sleep: davinci-mdio-sleep-pins {
290 pinctrl-single,pins = <
291 /* MDIO reset value */
292 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
293 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
294 >;
295 };
296
297 mmc1_pins: mmc1-pins {
298 pinctrl-single,pins = <
299 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
300 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
301 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
302 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
303 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
304 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
305 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
306 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
307 >;
308 };
309
310 mmc3_pins: mmc3-pins {
311 pinctrl-single,pins = <
312 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
313 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
314 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
315 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
316 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
317 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
318 >;
319 };
320
321 wlan_pins: wlan-pins {
322 pinctrl-single,pins = <
323 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */
324 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
325 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
326 >;
327 };
328
329 lcd_pins_s0: lcd-s0-pins {
330 pinctrl-single,pins = <
331 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */
332 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */
333 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */
334 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */
335 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */
336 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */
337 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */
338 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */
339 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
340 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
341 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
342 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
343 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
344 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
345 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
346 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
347 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
348 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
349 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
350 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
351 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
352 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
353 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
354 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
355 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
356 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
357 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
358 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
359 >;
360 };
361
362 mcasp1_pins: mcasp1-pins {
363 pinctrl-single,pins = <
364 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
365 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
366 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
367 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
368 >;
369 };
370
371 mcasp1_pins_sleep: mcasp1-sleep-pins {
372 pinctrl-single,pins = <
373 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
374 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
375 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
376 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
377 >;
378 };
379
380 dcan1_pins_default: dcan1-default-pins {
381 pinctrl-single,pins = <
382 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
383 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
384 >;
385 };
386 };
387
388 &uart0 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart0_pins>;
391
392 status = "okay";
393 };
394
395 &uart1 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart1_pins>;
398
399 status = "okay";
400 };
401
402 &i2c0 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c0_pins>;
405
406 status = "okay";
407 clock-frequency = <400000>;
408
409 tps: tps@2d {
410 reg = <0x2d>;
411 };
412 };
413
414 &usb1 {
415 dr_mode = "host";
416 };
417
418 &i2c1 {
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c1_pins>;
421
422 status = "okay";
423 clock-frequency = <100000>;
424
425 lis331dlh: lis331dlh@18 {
426 compatible = "st,lis331dlh", "st,lis3lv02d";
427 reg = <0x18>;
428 Vdd-supply = <&lis3_reg>;
429 Vdd_IO-supply = <&lis3_reg>;
430
431 st,click-single-x;
432 st,click-single-y;
433 st,click-single-z;
434 st,click-thresh-x = <10>;
435 st,click-thresh-y = <10>;
436 st,click-thresh-z = <10>;
437 st,irq1-click;
438 st,irq2-click;
439 st,wakeup-x-lo;
440 st,wakeup-x-hi;
441 st,wakeup-y-lo;
442 st,wakeup-y-hi;
443 st,wakeup-z-lo;
444 st,wakeup-z-hi;
445 st,min-limit-x = <120>;
446 st,min-limit-y = <120>;
447 st,min-limit-z = <140>;
448 st,max-limit-x = <550>;
449 st,max-limit-y = <550>;
450 st,max-limit-z = <750>;
451 };
452
453 tsl2550: tsl2550@39 {
454 compatible = "taos,tsl2550";
455 reg = <0x39>;
456 };
457
458 tmp275: tmp275@48 {
459 compatible = "ti,tmp275";
460 reg = <0x48>;
461 };
462
463 tlv320aic3106: tlv320aic3106@1b {
464 #sound-dai-cells = <0>;
465 compatible = "ti,tlv320aic3106";
466 reg = <0x1b>;
467 status = "okay";
468
469 /* Regulators */
470 AVDD-supply = <&v3_3d_reg>;
471 IOVDD-supply = <&v3_3d_reg>;
472 DRVDD-supply = <&v3_3d_reg>;
473 DVDD-supply = <&v1_8d_reg>;
474 };
475 };
476
477 &lcdc {
478 status = "okay";
479
480 blue-and-red-wiring = "crossed";
481
482 port {
483 lcdc_0: endpoint@0 {
484 remote-endpoint = <&panel_0>;
485 };
486 };
487 };
488
489 &elm {
490 status = "okay";
491 };
492
493 &epwmss0 {
494 status = "okay";
495
496 ecap0: pwm@100 {
497 status = "okay";
498 pinctrl-names = "default";
499 pinctrl-0 = <&ecap0_pins>;
500 };
501 };
502
503 &gpmc {
504 status = "okay";
505 pinctrl-names = "default";
506 pinctrl-0 = <&nandflash_pins_s0>;
507 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
508 nand@0,0 {
509 compatible = "ti,omap2-nand";
510 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
511 interrupt-parent = <&gpmc>;
512 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
513 <1 IRQ_TYPE_NONE>; /* termcount */
514 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
515 ti,nand-xfer-type = "prefetch-dma";
516 ti,nand-ecc-opt = "bch8";
517 ti,elm-id = <&elm>;
518 nand-bus-width = <8>;
519 gpmc,device-width = <1>;
520 gpmc,sync-clk-ps = <0>;
521 gpmc,cs-on-ns = <0>;
522 gpmc,cs-rd-off-ns = <44>;
523 gpmc,cs-wr-off-ns = <44>;
524 gpmc,adv-on-ns = <6>;
525 gpmc,adv-rd-off-ns = <34>;
526 gpmc,adv-wr-off-ns = <44>;
527 gpmc,we-on-ns = <0>;
528 gpmc,we-off-ns = <40>;
529 gpmc,oe-on-ns = <0>;
530 gpmc,oe-off-ns = <54>;
531 gpmc,access-ns = <64>;
532 gpmc,rd-cycle-ns = <82>;
533 gpmc,wr-cycle-ns = <82>;
534 gpmc,bus-turnaround-ns = <0>;
535 gpmc,cycle2cycle-delay-ns = <0>;
536 gpmc,clk-activation-ns = <0>;
537 gpmc,wr-access-ns = <40>;
538 gpmc,wr-data-mux-bus-ns = <0>;
539 /* MTD partition table */
540 /* All SPL-* partitions are sized to minimal length
541 * which can be independently programmable. For
542 * NAND flash this is equal to size of erase-block */
543 #address-cells = <1>;
544 #size-cells = <1>;
545 partition@0 {
546 label = "NAND.SPL";
547 reg = <0x00000000 0x00020000>;
548 };
549 partition@1 {
550 label = "NAND.SPL.backup1";
551 reg = <0x00020000 0x00020000>;
552 };
553 partition@2 {
554 label = "NAND.SPL.backup2";
555 reg = <0x00040000 0x00020000>;
556 };
557 partition@3 {
558 label = "NAND.SPL.backup3";
559 reg = <0x00060000 0x00020000>;
560 };
561 partition@4 {
562 label = "NAND.u-boot-spl-os";
563 reg = <0x00080000 0x00040000>;
564 };
565 partition@5 {
566 label = "NAND.u-boot";
567 reg = <0x000C0000 0x00100000>;
568 };
569 partition@6 {
570 label = "NAND.u-boot-env";
571 reg = <0x001C0000 0x00020000>;
572 };
573 partition@7 {
574 label = "NAND.u-boot-env.backup1";
575 reg = <0x001E0000 0x00020000>;
576 };
577 partition@8 {
578 label = "NAND.kernel";
579 reg = <0x00200000 0x00800000>;
580 };
581 partition@9 {
582 label = "NAND.file-system";
583 reg = <0x00A00000 0x0F600000>;
584 };
585 };
586 };
587
588 #include "../../tps65910.dtsi"
589
590 &mcasp1 {
591 #sound-dai-cells = <0>;
592 pinctrl-names = "default", "sleep";
593 pinctrl-0 = <&mcasp1_pins>;
594 pinctrl-1 = <&mcasp1_pins_sleep>;
595
596 status = "okay";
597
598 op-mode = <0>; /* MCASP_IIS_MODE */
599 tdm-slots = <2>;
600 /* 4 serializers */
601 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
602 0 0 1 2
603 >;
604 tx-num-evt = <32>;
605 rx-num-evt = <32>;
606 };
607
608 &tps {
609 vcc1-supply = <&vbat>;
610 vcc2-supply = <&vbat>;
611 vcc3-supply = <&vbat>;
612 vcc4-supply = <&vbat>;
613 vcc5-supply = <&vbat>;
614 vcc6-supply = <&vbat>;
615 vcc7-supply = <&vbat>;
616 vccio-supply = <&vbat>;
617
618 regulators {
619 vrtc_reg: regulator@0 {
620 regulator-always-on;
621 };
622
623 vio_reg: regulator@1 {
624 regulator-always-on;
625 };
626
627 vdd1_reg: regulator@2 {
628 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
629 regulator-name = "vdd_mpu";
630 regulator-min-microvolt = <912500>;
631 regulator-max-microvolt = <1351500>;
632 regulator-boot-on;
633 regulator-always-on;
634 };
635
636 vdd2_reg: regulator@3 {
637 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
638 regulator-name = "vdd_core";
639 regulator-min-microvolt = <912500>;
640 regulator-max-microvolt = <1150000>;
641 regulator-boot-on;
642 regulator-always-on;
643 };
644
645 vdd3_reg: regulator@4 {
646 regulator-always-on;
647 };
648
649 vdig1_reg: regulator@5 {
650 regulator-always-on;
651 };
652
653 vdig2_reg: regulator@6 {
654 regulator-always-on;
655 };
656
657 vpll_reg: regulator@7 {
658 regulator-always-on;
659 };
660
661 vdac_reg: regulator@8 {
662 regulator-always-on;
663 };
664
665 vaux1_reg: regulator@9 {
666 regulator-always-on;
667 };
668
669 vaux2_reg: regulator@10 {
670 regulator-always-on;
671 };
672
673 vaux33_reg: regulator@11 {
674 regulator-always-on;
675 };
676
677 vmmc_reg: regulator@12 {
678 regulator-min-microvolt = <1800000>;
679 regulator-max-microvolt = <3300000>;
680 regulator-always-on;
681 };
682 };
683 };
684
685 &mac_sw {
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&cpsw_default>;
688 pinctrl-1 = <&cpsw_sleep>;
689 status = "okay";
690 };
691
692 &davinci_mdio_sw {
693 pinctrl-names = "default", "sleep";
694 pinctrl-0 = <&davinci_mdio_default>;
695 pinctrl-1 = <&davinci_mdio_sleep>;
696
697 ethphy0: ethernet-phy@0 {
698 reg = <0>;
699 };
700 };
701
702 &cpsw_port1 {
703 phy-handle = <ðphy0>;
704 phy-mode = "rgmii-id";
705 ti,dual-emac-pvid = <1>;
706 };
707
708 &cpsw_port2 {
709 status = "disabled";
710 };
711
712 &tscadc {
713 status = "okay";
714 tsc {
715 ti,wires = <4>;
716 ti,x-plate-resistance = <200>;
717 ti,coordinate-readouts = <5>;
718 ti,wire-config = <0x00 0x11 0x22 0x33>;
719 ti,charge-delay = <0x400>;
720 };
721
722 adc {
723 ti,adc-channels = <4 5 6 7>;
724 };
725 };
726
727 &mmc1 {
728 status = "okay";
729 vmmc-supply = <&vmmc_reg>;
730 bus-width = <4>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&mmc1_pins>;
733 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
734 };
735
736 &mmc3 {
737 /* these are on the crossbar and are outlined in the
738 xbar-event-map element */
739 dmas = <&edma_xbar 12 0 1
740 &edma_xbar 13 0 2>;
741 dma-names = "tx", "rx";
742 status = "okay";
743 vmmc-supply = <&wlan_en_reg>;
744 bus-width = <4>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&mmc3_pins &wlan_pins>;
747 non-removable;
748 cap-power-off-card;
749 keep-power-in-suspend;
750
751 #address-cells = <1>;
752 #size-cells = <0>;
753 wlcore: wlcore@0 {
754 compatible = "ti,wl1835";
755 reg = <2>;
756 interrupt-parent = <&gpio3>;
757 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
758 };
759 };
760
761 &sham {
762 status = "okay";
763 };
764
765 &aes {
766 status = "okay";
767 };
768
769 &dcan1 {
770 status = "disabled"; /* Enable only if Profile 1 is selected */
771 pinctrl-names = "default";
772 pinctrl-0 = <&dcan1_pins_default>;
773 };
774
775 &rtc {
776 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
777 clock-names = "ext-clk", "int-clk";
778 };
779
780 &pruss_tm {
781 status = "okay";
782 };
783
784 &wkup_m3_ipc {
785 firmware-name = "am335x-evm-scale-data.bin";
786 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.