1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
4 *
5 * Authors: SZ Lin (林上智) <sz.lin@moxa.com>
6 * Wes Huang (黃淵河) <wes.huang@moxa.com>
7 * Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
8 */
9
10 /dts-v1/;
11
12 #include "am335x-moxa-uc-2100-common.dtsi"
13
14 / {
15 model = "Moxa UC-2101";
16 compatible = "moxa,uc-2101", "ti,am33xx";
17
18 leds {
19 compatible = "gpio-leds";
20 led1 {
21 label = "UC2100:GREEN:USER";
22 gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
23 default-state = "off";
24 };
25 };
26 };
27
28 &am33xx_pinmux {
29 pinctrl-names = "default";
30
31 cpsw_default: cpsw-default-pins {
32 pinctrl-single,pins = <
33 /* Slave 1 */
34 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
35 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
36 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */
37 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
38 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
39 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
40 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
41 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
42 >;
43 };
44
45 spi1_pins: spi1-pins {
46 pinctrl-single,pins = <
47 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */
48 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */
49 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */
50 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */
51 >;
52 };
53 };
54
55 &davinci_mdio_sw {
56 phy0: ethernet-phy@4 {
57 reg = <4>;
58 };
59 };
60
61 &cpsw_port1 {
62 phy-handle = <&phy0>;
63 phy-mode = "rmii";
64 };
65
66 &cpsw_port2 {
67 status = "disabled";
68 };
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