1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Device Tree Source for AM33xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7 &scm_clocks {
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
12 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
13 ti,bit-shift = <22>;
14 reg = <0x0040>;
15 };
16
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
21 clocks = <&sys_clkin_ck>;
22 clock-mult = <1>;
23 clock-div = <1>;
24 };
25
26 dcan0_fck: clock-dcan0-fck {
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
29 clock-output-names = "dcan0_fck";
30 clocks = <&sys_clkin_ck>;
31 clock-mult = <1>;
32 clock-div = <1>;
33 };
34
35 dcan1_fck: clock-dcan1-fck {
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
38 clock-output-names = "dcan1_fck";
39 clocks = <&sys_clkin_ck>;
40 clock-mult = <1>;
41 clock-div = <1>;
42 };
43
44 mcasp0_fck: clock-mcasp0-fck {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
47 clock-output-names = "mcasp0_fck";
48 clocks = <&sys_clkin_ck>;
49 clock-mult = <1>;
50 clock-div = <1>;
51 };
52
53 mcasp1_fck: clock-mcasp1-fck {
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
56 clock-output-names = "mcasp1_fck";
57 clocks = <&sys_clkin_ck>;
58 clock-mult = <1>;
59 clock-div = <1>;
60 };
61
62 smartreflex0_fck: clock-smartreflex0-fck {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-output-names = "smartreflex0_fck";
66 clocks = <&sys_clkin_ck>;
67 clock-mult = <1>;
68 clock-div = <1>;
69 };
70
71 smartreflex1_fck: clock-smartreflex1-fck {
72 #clock-cells = <0>;
73 compatible = "fixed-factor-clock";
74 clock-output-names = "smartreflex1_fck";
75 clocks = <&sys_clkin_ck>;
76 clock-mult = <1>;
77 clock-div = <1>;
78 };
79
80 sha0_fck: clock-sha0-fck {
81 #clock-cells = <0>;
82 compatible = "fixed-factor-clock";
83 clock-output-names = "sha0_fck";
84 clocks = <&sys_clkin_ck>;
85 clock-mult = <1>;
86 clock-div = <1>;
87 };
88
89 aes0_fck: clock-aes0-fck {
90 #clock-cells = <0>;
91 compatible = "fixed-factor-clock";
92 clock-output-names = "aes0_fck";
93 clocks = <&sys_clkin_ck>;
94 clock-mult = <1>;
95 clock-div = <1>;
96 };
97
98 rng_fck: clock-rng-fck {
99 #clock-cells = <0>;
100 compatible = "fixed-factor-clock";
101 clock-output-names = "rng_fck";
102 clocks = <&sys_clkin_ck>;
103 clock-mult = <1>;
104 clock-div = <1>;
105 };
106
107 clock@664 {
108 compatible = "ti,clksel";
109 reg = <0x664>;
110 #clock-cells = <2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
115 reg = <0>;
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clock-output-names = "ehrpwm0_tbclk";
119 clocks = <&l4ls_gclk>;
120 };
121
122 ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
123 reg = <1>;
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clock-output-names = "ehrpwm1_tbclk";
127 clocks = <&l4ls_gclk>;
128 };
129
130 ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
131 reg = <2>;
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clock-output-names = "ehrpwm2_tbclk";
135 clocks = <&l4ls_gclk>;
136 };
137 };
138 };
139 &prcm_clocks {
140 clk_32768_ck: clock-clk-32768 {
141 #clock-cells = <0>;
142 compatible = "fixed-clock";
143 clock-output-names = "clk_32768_ck";
144 clock-frequency = <32768>;
145 };
146
147 clk_rc32k_ck: clock-clk-rc32k {
148 #clock-cells = <0>;
149 compatible = "fixed-clock";
150 clock-output-names = "clk_rc32k_ck";
151 clock-frequency = <32000>;
152 };
153
154 virt_19200000_ck: clock-virt-19200000 {
155 #clock-cells = <0>;
156 compatible = "fixed-clock";
157 clock-output-names = "virt_19200000_ck";
158 clock-frequency = <19200000>;
159 };
160
161 virt_24000000_ck: clock-virt-24000000 {
162 #clock-cells = <0>;
163 compatible = "fixed-clock";
164 clock-output-names = "virt_24000000_ck";
165 clock-frequency = <24000000>;
166 };
167
168 virt_25000000_ck: clock-virt-25000000 {
169 #clock-cells = <0>;
170 compatible = "fixed-clock";
171 clock-output-names = "virt_25000000_ck";
172 clock-frequency = <25000000>;
173 };
174
175 virt_26000000_ck: clock-virt-26000000 {
176 #clock-cells = <0>;
177 compatible = "fixed-clock";
178 clock-output-names = "virt_26000000_ck";
179 clock-frequency = <26000000>;
180 };
181
182 tclkin_ck: clock-tclkin {
183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-output-names = "tclkin_ck";
186 clock-frequency = <12000000>;
187 };
188
189 dpll_core_ck: clock@490 {
190 #clock-cells = <0>;
191 compatible = "ti,am3-dpll-core-clock";
192 clock-output-names = "dpll_core_ck";
193 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
194 reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
195 };
196
197 dpll_core_x2_ck: clock-dpll-core-x2 {
198 #clock-cells = <0>;
199 compatible = "ti,am3-dpll-x2-clock";
200 clock-output-names = "dpll_core_x2_ck";
201 clocks = <&dpll_core_ck>;
202 };
203
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
205 #clock-cells = <0>;
206 compatible = "ti,divider-clock";
207 clock-output-names = "dpll_core_m4_ck";
208 clocks = <&dpll_core_x2_ck>;
209 ti,max-div = <31>;
210 reg = <0x0480>;
211 ti,index-starts-at-one;
212 };
213
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
215 #clock-cells = <0>;
216 compatible = "ti,divider-clock";
217 clock-output-names = "dpll_core_m5_ck";
218 clocks = <&dpll_core_x2_ck>;
219 ti,max-div = <31>;
220 reg = <0x0484>;
221 ti,index-starts-at-one;
222 };
223
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
225 #clock-cells = <0>;
226 compatible = "ti,divider-clock";
227 clock-output-names = "dpll_core_m6_ck";
228 clocks = <&dpll_core_x2_ck>;
229 ti,max-div = <31>;
230 reg = <0x04d8>;
231 ti,index-starts-at-one;
232 };
233
234 dpll_mpu_ck: clock@488 {
235 #clock-cells = <0>;
236 compatible = "ti,am3-dpll-clock";
237 clock-output-names = "dpll_mpu_ck";
238 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
239 reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
240 };
241
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
243 #clock-cells = <0>;
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_mpu_m2_ck";
246 clocks = <&dpll_mpu_ck>;
247 ti,max-div = <31>;
248 reg = <0x04a8>;
249 ti,index-starts-at-one;
250 };
251
252 dpll_ddr_ck: clock@494 {
253 #clock-cells = <0>;
254 compatible = "ti,am3-dpll-no-gate-clock";
255 clock-output-names = "dpll_ddr_ck";
256 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
257 reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
258 };
259
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
261 #clock-cells = <0>;
262 compatible = "ti,divider-clock";
263 clock-output-names = "dpll_ddr_m2_ck";
264 clocks = <&dpll_ddr_ck>;
265 ti,max-div = <31>;
266 reg = <0x04a0>;
267 ti,index-starts-at-one;
268 };
269
270 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clock-output-names = "dpll_ddr_m2_div2_ck";
274 clocks = <&dpll_ddr_m2_ck>;
275 clock-mult = <1>;
276 clock-div = <2>;
277 };
278
279 dpll_disp_ck: clock@498 {
280 #clock-cells = <0>;
281 compatible = "ti,am3-dpll-no-gate-clock";
282 clock-output-names = "dpll_disp_ck";
283 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
284 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
285 };
286
287 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
288 #clock-cells = <0>;
289 compatible = "ti,divider-clock";
290 clock-output-names = "dpll_disp_m2_ck";
291 clocks = <&dpll_disp_ck>;
292 ti,max-div = <31>;
293 reg = <0x04a4>;
294 ti,index-starts-at-one;
295 ti,set-rate-parent;
296 };
297
298 dpll_per_ck: clock@48c {
299 #clock-cells = <0>;
300 compatible = "ti,am3-dpll-no-gate-j-type-clock";
301 clock-output-names = "dpll_per_ck";
302 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
303 reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
304 };
305
306 dpll_per_m2_ck: clock-dpll-per-m2@4ac {
307 #clock-cells = <0>;
308 compatible = "ti,divider-clock";
309 clock-output-names = "dpll_per_m2_ck";
310 clocks = <&dpll_per_ck>;
311 ti,max-div = <31>;
312 reg = <0x04ac>;
313 ti,index-starts-at-one;
314 };
315
316 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
317 #clock-cells = <0>;
318 compatible = "fixed-factor-clock";
319 clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
320 clocks = <&dpll_per_m2_ck>;
321 clock-mult = <1>;
322 clock-div = <4>;
323 };
324
325 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
326 #clock-cells = <0>;
327 compatible = "fixed-factor-clock";
328 clock-output-names = "dpll_per_m2_div4_ck";
329 clocks = <&dpll_per_m2_ck>;
330 clock-mult = <1>;
331 clock-div = <4>;
332 };
333
334 clk_24mhz: clock-clk-24mhz {
335 #clock-cells = <0>;
336 compatible = "fixed-factor-clock";
337 clock-output-names = "clk_24mhz";
338 clocks = <&dpll_per_m2_ck>;
339 clock-mult = <1>;
340 clock-div = <8>;
341 };
342
343 clkdiv32k_ck: clock-clkdiv32k {
344 #clock-cells = <0>;
345 compatible = "fixed-factor-clock";
346 clock-output-names = "clkdiv32k_ck";
347 clocks = <&clk_24mhz>;
348 clock-mult = <1>;
349 clock-div = <732>;
350 };
351
352 l3_gclk: clock-l3-gclk {
353 #clock-cells = <0>;
354 compatible = "fixed-factor-clock";
355 clock-output-names = "l3_gclk";
356 clocks = <&dpll_core_m4_ck>;
357 clock-mult = <1>;
358 clock-div = <1>;
359 };
360
361 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
362 #clock-cells = <0>;
363 compatible = "ti,mux-clock";
364 clock-output-names = "pruss_ocp_gclk";
365 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
366 reg = <0x0530>;
367 };
368
369 mmu_fck: clock-mmu-fck-1@914 {
370 #clock-cells = <0>;
371 compatible = "ti,gate-clock";
372 clock-output-names = "mmu_fck";
373 clocks = <&dpll_core_m4_ck>;
374 ti,bit-shift = <1>;
375 reg = <0x0914>;
376 };
377
378 timer1_fck: clock-timer1-fck@528 {
379 #clock-cells = <0>;
380 compatible = "ti,mux-clock";
381 clock-output-names = "timer1_fck";
382 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
383 reg = <0x0528>;
384 };
385
386 timer2_fck: clock-timer2-fck@508 {
387 #clock-cells = <0>;
388 compatible = "ti,mux-clock";
389 clock-output-names = "timer2_fck";
390 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
391 reg = <0x0508>;
392 };
393
394 timer3_fck: clock-timer3-fck@50c {
395 #clock-cells = <0>;
396 compatible = "ti,mux-clock";
397 clock-output-names = "timer3_fck";
398 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
399 reg = <0x050c>;
400 };
401
402 timer4_fck: clock-timer4-fck@510 {
403 #clock-cells = <0>;
404 compatible = "ti,mux-clock";
405 clock-output-names = "timer4_fck";
406 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
407 reg = <0x0510>;
408 };
409
410 timer5_fck: clock-timer5-fck@518 {
411 #clock-cells = <0>;
412 compatible = "ti,mux-clock";
413 clock-output-names = "timer5_fck";
414 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
415 reg = <0x0518>;
416 };
417
418 timer6_fck: clock-timer6-fck@51c {
419 #clock-cells = <0>;
420 compatible = "ti,mux-clock";
421 clock-output-names = "timer6_fck";
422 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
423 reg = <0x051c>;
424 };
425
426 timer7_fck: clock-timer7-fck@504 {
427 #clock-cells = <0>;
428 compatible = "ti,mux-clock";
429 clock-output-names = "timer7_fck";
430 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
431 reg = <0x0504>;
432 };
433
434 usbotg_fck: clock-usbotg-fck-8@47c {
435 #clock-cells = <0>;
436 compatible = "ti,gate-clock";
437 clock-output-names = "usbotg_fck";
438 clocks = <&dpll_per_ck>;
439 ti,bit-shift = <8>;
440 reg = <0x047c>;
441 };
442
443 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
444 #clock-cells = <0>;
445 compatible = "fixed-factor-clock";
446 clock-output-names = "dpll_core_m4_div2_ck";
447 clocks = <&dpll_core_m4_ck>;
448 clock-mult = <1>;
449 clock-div = <2>;
450 };
451
452 ieee5000_fck: clock-ieee5000-fck-1@e4 {
453 #clock-cells = <0>;
454 compatible = "ti,gate-clock";
455 clock-output-names = "ieee5000_fck";
456 clocks = <&dpll_core_m4_div2_ck>;
457 ti,bit-shift = <1>;
458 reg = <0x00e4>;
459 };
460
461 wdt1_fck: clock-wdt1-fck@538 {
462 #clock-cells = <0>;
463 compatible = "ti,mux-clock";
464 clock-output-names = "wdt1_fck";
465 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
466 reg = <0x0538>;
467 };
468
469 l4_rtc_gclk: clock-l4-rtc-gclk {
470 #clock-cells = <0>;
471 compatible = "fixed-factor-clock";
472 clock-output-names = "l4_rtc_gclk";
473 clocks = <&dpll_core_m4_ck>;
474 clock-mult = <1>;
475 clock-div = <2>;
476 };
477
478 l4hs_gclk: clock-l4hs-gclk {
479 #clock-cells = <0>;
480 compatible = "fixed-factor-clock";
481 clock-output-names = "l4hs_gclk";
482 clocks = <&dpll_core_m4_ck>;
483 clock-mult = <1>;
484 clock-div = <1>;
485 };
486
487 l3s_gclk: clock-l3s-gclk {
488 #clock-cells = <0>;
489 compatible = "fixed-factor-clock";
490 clock-output-names = "l3s_gclk";
491 clocks = <&dpll_core_m4_div2_ck>;
492 clock-mult = <1>;
493 clock-div = <1>;
494 };
495
496 l4fw_gclk: clock-l4fw-gclk {
497 #clock-cells = <0>;
498 compatible = "fixed-factor-clock";
499 clock-output-names = "l4fw_gclk";
500 clocks = <&dpll_core_m4_div2_ck>;
501 clock-mult = <1>;
502 clock-div = <1>;
503 };
504
505 l4ls_gclk: clock-l4ls-gclk {
506 #clock-cells = <0>;
507 compatible = "fixed-factor-clock";
508 clock-output-names = "l4ls_gclk";
509 clocks = <&dpll_core_m4_div2_ck>;
510 clock-mult = <1>;
511 clock-div = <1>;
512 };
513
514 sysclk_div_ck: clock-sysclk-div {
515 #clock-cells = <0>;
516 compatible = "fixed-factor-clock";
517 clock-output-names = "sysclk_div_ck";
518 clocks = <&dpll_core_m4_ck>;
519 clock-mult = <1>;
520 clock-div = <1>;
521 };
522
523 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
524 #clock-cells = <0>;
525 compatible = "fixed-factor-clock";
526 clock-output-names = "cpsw_125mhz_gclk";
527 clocks = <&dpll_core_m5_ck>;
528 clock-mult = <1>;
529 clock-div = <2>;
530 };
531
532 cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
533 #clock-cells = <0>;
534 compatible = "ti,mux-clock";
535 clock-output-names = "cpsw_cpts_rft_clk";
536 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
537 reg = <0x0520>;
538 };
539
540 gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
541 #clock-cells = <0>;
542 compatible = "ti,mux-clock";
543 clock-output-names = "gpio0_dbclk_mux_ck";
544 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
545 reg = <0x053c>;
546 };
547
548 lcd_gclk: clock-lcd-gclk@534 {
549 #clock-cells = <0>;
550 compatible = "ti,mux-clock";
551 clock-output-names = "lcd_gclk";
552 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
553 reg = <0x0534>;
554 ti,set-rate-parent;
555 };
556
557 mmc_clk: clock-mmc {
558 #clock-cells = <0>;
559 compatible = "fixed-factor-clock";
560 clock-output-names = "mmc_clk";
561 clocks = <&dpll_per_m2_ck>;
562 clock-mult = <1>;
563 clock-div = <2>;
564 };
565
566 clock@52c {
567 compatible = "ti,clksel";
568 reg = <0x52c>;
569 #clock-cells = <2>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572
573 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
574 reg = <1>;
575 #clock-cells = <0>;
576 compatible = "ti,mux-clock";
577 clock-output-names = "gfx_fclk_clksel_ck";
578 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
579 };
580
581 gfx_fck_div_ck: clock-gfx-fck-div@0 {
582 reg = <0>;
583 #clock-cells = <0>;
584 compatible = "ti,divider-clock";
585 clock-output-names = "gfx_fck_div_ck";
586 clocks = <&gfx_fclk_clksel_ck>;
587 ti,max-div = <2>;
588 };
589 };
590
591 clock@700 {
592 compatible = "ti,clksel";
593 reg = <0x700>;
594 #clock-cells = <2>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597
598 sysclkout_pre_ck: clock-sysclkout-pre@0 {
599 reg = <0>;
600 #clock-cells = <0>;
601 compatible = "ti,mux-clock";
602 clock-output-names = "sysclkout_pre_ck";
603 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
604 };
605
606 clkout2_div_ck: clock-clkout2-div@3 {
607 reg = <3>;
608 #clock-cells = <0>;
609 compatible = "ti,divider-clock";
610 clock-output-names = "clkout2_div_ck";
611 clocks = <&sysclkout_pre_ck>;
612 ti,max-div = <8>;
613 };
614
615 clkout2_ck: clock-clkout2@7 {
616 reg = <7>;
617 #clock-cells = <0>;
618 compatible = "ti,gate-clock";
619 clock-output-names = "clkout2_ck";
620 clocks = <&clkout2_div_ck>;
621 };
622 };
623 };
624
625 &prcm {
626 per_cm: clock@0 {
627 compatible = "ti,omap4-cm";
628 clock-output-names = "per_cm";
629 reg = <0x0 0x400>;
630 #address-cells = <1>;
631 #size-cells = <1>;
632 ranges = <0 0x0 0x400>;
633
634 l4ls_clkctrl: clock@38 {
635 compatible = "ti,clkctrl";
636 clock-output-names = "l4ls_clkctrl";
637 reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
638 #clock-cells = <2>;
639 };
640
641 l3s_clkctrl: clock@1c {
642 compatible = "ti,clkctrl";
643 clock-output-names = "l3s_clkctrl";
644 reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
645 #clock-cells = <2>;
646 };
647
648 l3_clkctrl: clock@24 {
649 compatible = "ti,clkctrl";
650 clock-output-names = "l3_clkctrl";
651 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
652 #clock-cells = <2>;
653 };
654
655 l4hs_clkctrl: clock@120 {
656 compatible = "ti,clkctrl";
657 clock-output-names = "l4hs_clkctrl";
658 reg = <0x120 0x4>;
659 #clock-cells = <2>;
660 };
661
662 pruss_ocp_clkctrl: clock@e8 {
663 compatible = "ti,clkctrl";
664 clock-output-names = "pruss_ocp_clkctrl";
665 reg = <0xe8 0x4>;
666 #clock-cells = <2>;
667 };
668
669 cpsw_125mhz_clkctrl: clock@0 {
670 compatible = "ti,clkctrl";
671 clock-output-names = "cpsw_125mhz_clkctrl";
672 reg = <0x0 0x18>;
673 #clock-cells = <2>;
674 };
675
676 lcdc_clkctrl: clock@18 {
677 compatible = "ti,clkctrl";
678 clock-output-names = "lcdc_clkctrl";
679 reg = <0x18 0x4>;
680 #clock-cells = <2>;
681 };
682
683 clk_24mhz_clkctrl: clock@14c {
684 compatible = "ti,clkctrl";
685 clock-output-names = "clk_24mhz_clkctrl";
686 reg = <0x14c 0x4>;
687 #clock-cells = <2>;
688 };
689 };
690
691 wkup_cm: clock@400 {
692 compatible = "ti,omap4-cm";
693 clock-output-names = "wkup_cm";
694 reg = <0x400 0x100>;
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges = <0 0x400 0x100>;
698
699 l4_wkup_clkctrl: clock@0 {
700 compatible = "ti,clkctrl";
701 clock-output-names = "l4_wkup_clkctrl";
702 reg = <0x0 0x10>, <0xb4 0x24>;
703 #clock-cells = <2>;
704 };
705
706 l3_aon_clkctrl: clock@14 {
707 compatible = "ti,clkctrl";
708 clock-output-names = "l3_aon_clkctrl";
709 reg = <0x14 0x4>;
710 #clock-cells = <2>;
711 };
712
713 l4_wkup_aon_clkctrl: clock@b0 {
714 compatible = "ti,clkctrl";
715 clock-output-names = "l4_wkup_aon_clkctrl";
716 reg = <0xb0 0x4>;
717 #clock-cells = <2>;
718 };
719 };
720
721 mpu_cm: clock@600 {
722 compatible = "ti,omap4-cm";
723 clock-output-names = "mpu_cm";
724 reg = <0x600 0x100>;
725 #address-cells = <1>;
726 #size-cells = <1>;
727 ranges = <0 0x600 0x100>;
728
729 mpu_clkctrl: clock@0 {
730 compatible = "ti,clkctrl";
731 clock-output-names = "mpu_clkctrl";
732 reg = <0x0 0x8>;
733 #clock-cells = <2>;
734 };
735 };
736
737 l4_rtc_cm: clock@800 {
738 compatible = "ti,omap4-cm";
739 clock-output-names = "l4_rtc_cm";
740 reg = <0x800 0x100>;
741 #address-cells = <1>;
742 #size-cells = <1>;
743 ranges = <0 0x800 0x100>;
744
745 l4_rtc_clkctrl: clock@0 {
746 compatible = "ti,clkctrl";
747 clock-output-names = "l4_rtc_clkctrl";
748 reg = <0x0 0x4>;
749 #clock-cells = <2>;
750 };
751 };
752
753 gfx_l3_cm: clock@900 {
754 compatible = "ti,omap4-cm";
755 clock-output-names = "gfx_l3_cm";
756 reg = <0x900 0x100>;
757 #address-cells = <1>;
758 #size-cells = <1>;
759 ranges = <0 0x900 0x100>;
760
761 gfx_l3_clkctrl: clock@0 {
762 compatible = "ti,clkctrl";
763 clock-output-names = "gfx_l3_clkctrl";
764 reg = <0x0 0x8>;
765 #clock-cells = <2>;
766 };
767 };
768
769 l4_cefuse_cm: clock@a00 {
770 compatible = "ti,omap4-cm";
771 clock-output-names = "l4_cefuse_cm";
772 reg = <0xa00 0x100>;
773 #address-cells = <1>;
774 #size-cells = <1>;
775 ranges = <0 0xa00 0x100>;
776
777 l4_cefuse_clkctrl: clock@0 {
778 compatible = "ti,clkctrl";
779 clock-output-names = "l4_cefuse_clkctrl";
780 reg = <0x0 0x24>;
781 #clock-cells = <2>;
782 };
783 };
784 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.