1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7 &prm_clocks {
8 corex2_d3_fck: corex2_d3_fck {
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
11 clocks = <&corex2_fck>;
12 clock-mult = <1>;
13 clock-div = <3>;
14 };
15
16 corex2_d5_fck: corex2_d5_fck {
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
19 clocks = <&corex2_fck>;
20 clock-mult = <1>;
21 clock-div = <5>;
22 };
23 };
24 &cm_clocks {
25 dpll5_ck: dpll5_ck@d04 {
26 #clock-cells = <0>;
27 compatible = "ti,omap3-dpll-clock";
28 clocks = <&sys_ck>, <&sys_ck>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
30 ti,low-power-stop;
31 ti,lock;
32 };
33
34 dpll5_m2_ck: dpll5_m2_ck@d50 {
35 #clock-cells = <0>;
36 compatible = "ti,divider-clock";
37 clocks = <&dpll5_ck>;
38 ti,max-div = <31>;
39 reg = <0x0d50>;
40 ti,index-starts-at-one;
41 };
42
43 sgx_gate_fck: sgx_gate_fck@b00 {
44 #clock-cells = <0>;
45 compatible = "ti,composite-gate-clock";
46 clocks = <&core_ck>;
47 ti,bit-shift = <1>;
48 reg = <0x0b00>;
49 };
50
51 core_d3_ck: core_d3_ck {
52 #clock-cells = <0>;
53 compatible = "fixed-factor-clock";
54 clocks = <&core_ck>;
55 clock-mult = <1>;
56 clock-div = <3>;
57 };
58
59 core_d4_ck: core_d4_ck {
60 #clock-cells = <0>;
61 compatible = "fixed-factor-clock";
62 clocks = <&core_ck>;
63 clock-mult = <1>;
64 clock-div = <4>;
65 };
66
67 core_d6_ck: core_d6_ck {
68 #clock-cells = <0>;
69 compatible = "fixed-factor-clock";
70 clocks = <&core_ck>;
71 clock-mult = <1>;
72 clock-div = <6>;
73 };
74
75 omap_192m_alwon_fck: omap_192m_alwon_fck {
76 #clock-cells = <0>;
77 compatible = "fixed-factor-clock";
78 clocks = <&dpll4_m2x2_ck>;
79 clock-mult = <1>;
80 clock-div = <1>;
81 };
82
83 core_d2_ck: core_d2_ck {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&core_ck>;
87 clock-mult = <1>;
88 clock-div = <2>;
89 };
90
91 sgx_mux_fck: sgx_mux_fck@b40 {
92 #clock-cells = <0>;
93 compatible = "ti,composite-mux-clock";
94 clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
95 reg = <0x0b40>;
96 };
97
98 sgx_fck: sgx_fck {
99 #clock-cells = <0>;
100 compatible = "ti,composite-clock";
101 clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
102 };
103
104 sgx_ick: sgx_ick@b10 {
105 #clock-cells = <0>;
106 compatible = "ti,wait-gate-clock";
107 clocks = <&l3_ick>;
108 reg = <0x0b10>;
109 ti,bit-shift = <0>;
110 };
111
112 cpefuse_fck: cpefuse_fck@a08 {
113 #clock-cells = <0>;
114 compatible = "ti,gate-clock";
115 clocks = <&sys_ck>;
116 reg = <0x0a08>;
117 ti,bit-shift = <0>;
118 };
119
120 ts_fck: ts_fck@a08 {
121 #clock-cells = <0>;
122 compatible = "ti,gate-clock";
123 clocks = <&omap_32k_fck>;
124 reg = <0x0a08>;
125 ti,bit-shift = <1>;
126 };
127
128 usbtll_fck: usbtll_fck@a08 {
129 #clock-cells = <0>;
130 compatible = "ti,wait-gate-clock";
131 clocks = <&dpll5_m2_ck>;
132 reg = <0x0a08>;
133 ti,bit-shift = <2>;
134 };
135
136 /* CM_ICLKEN3_CORE */
137 clock@a18 {
138 compatible = "ti,clksel";
139 reg = <0xa18>;
140 #clock-cells = <2>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 usbtll_ick: clock-usbtll-ick@2 {
145 reg = <2>;
146 #clock-cells = <0>;
147 compatible = "ti,omap3-interface-clock";
148 clock-output-names = "usbtll_ick";
149 clocks = <&core_l4_ick>;
150 };
151 };
152
153 clock@a10 {
154 compatible = "ti,clksel";
155 reg = <0xa10>;
156 #clock-cells = <2>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 mmchs3_ick: clock-mmchs3-ick@30 {
161 reg = <30>;
162 #clock-cells = <0>;
163 compatible = "ti,omap3-interface-clock";
164 clock-output-names = "mmchs3_ick";
165 clocks = <&core_l4_ick>;
166 };
167 };
168
169 clock@a00 {
170 compatible = "ti,clksel";
171 reg = <0xa00>;
172 #clock-cells = <2>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175
176 mmchs3_fck: clock-mmchs3-fck@30 {
177 reg = <30>;
178 #clock-cells = <0>;
179 compatible = "ti,wait-gate-clock";
180 clock-output-names = "mmchs3_fck";
181 clocks = <&core_96m_fck>;
182 };
183 };
184
185 clock@e00 {
186 compatible = "ti,clksel";
187 reg = <0xe00>;
188 #clock-cells = <2>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191
192 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
193 reg = <0>;
194 #clock-cells = <0>;
195 compatible = "ti,dss-gate-clock";
196 clock-output-names = "dss1_alwon_fck_3430es2";
197 clocks = <&dpll4_m4x2_ck>;
198 ti,set-rate-parent;
199 };
200 };
201
202 dss_ick: dss_ick_3430es2@e10 {
203 #clock-cells = <0>;
204 compatible = "ti,omap3-dss-interface-clock";
205 clocks = <&l4_ick>;
206 reg = <0x0e10>;
207 ti,bit-shift = <0>;
208 };
209
210 usbhost_120m_fck: usbhost_120m_fck@1400 {
211 #clock-cells = <0>;
212 compatible = "ti,gate-clock";
213 clocks = <&dpll5_m2_ck>;
214 reg = <0x1400>;
215 ti,bit-shift = <1>;
216 };
217
218 usbhost_48m_fck: usbhost_48m_fck@1400 {
219 #clock-cells = <0>;
220 compatible = "ti,dss-gate-clock";
221 clocks = <&omap_48m_fck>;
222 reg = <0x1400>;
223 ti,bit-shift = <0>;
224 };
225
226 usbhost_ick: usbhost_ick@1410 {
227 #clock-cells = <0>;
228 compatible = "ti,omap3-dss-interface-clock";
229 clocks = <&l4_ick>;
230 reg = <0x1410>;
231 ti,bit-shift = <0>;
232 };
233 };
234
235 &cm_clockdomains {
236 dpll5_clkdm: dpll5_clkdm {
237 compatible = "ti,clockdomain";
238 clocks = <&dpll5_ck>;
239 };
240
241 sgx_clkdm: sgx_clkdm {
242 compatible = "ti,clockdomain";
243 clocks = <&sgx_ick>;
244 };
245
246 dss_clkdm: dss_clkdm {
247 compatible = "ti,clockdomain";
248 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
249 <&dss1_alwon_fck>, <&dss_ick>;
250 };
251
252 core_l4_clkdm: core_l4_clkdm {
253 compatible = "ti,clockdomain";
254 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
255 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
256 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
257 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
258 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
259 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
260 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
261 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
262 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
263 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
264 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
265 };
266
267 usbhost_clkdm: usbhost_clkdm {
268 compatible = "ti,clockdomain";
269 clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
270 <&usbhost_ick>;
271 };
272 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.