1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7 &cm_clocks {
8 clock@a00 {
9 compatible = "ti,clksel";
10 reg = <0xa00>;
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
16 reg = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
20 clocks = <&corex2_fck>;
21 };
22 };
23
24 clock@a40 {
25 compatible = "ti,clksel";
26 reg = <0xa40>;
27 #clock-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
32 reg = <8>;
33 #clock-cells = <0>;
34 compatible = "ti,composite-divider-clock";
35 clock-output-names = "ssi_ssr_div_fck_3430es2";
36 clocks = <&corex2_fck>;
37 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
38 };
39 };
40
41 ssi_ssr_fck: ssi_ssr_fck_3430es2 {
42 #clock-cells = <0>;
43 compatible = "ti,composite-clock";
44 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
45 };
46
47 ssi_sst_fck: ssi_sst_fck_3430es2 {
48 #clock-cells = <0>;
49 compatible = "fixed-factor-clock";
50 clocks = <&ssi_ssr_fck>;
51 clock-mult = <1>;
52 clock-div = <2>;
53 };
54
55 clock@a10 {
56 compatible = "ti,clksel";
57 reg = <0xa10>;
58 #clock-cells = <2>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 {
63 reg = <4>;
64 #clock-cells = <0>;
65 compatible = "ti,omap3-hsotgusb-interface-clock";
66 clock-output-names = "hsotgusb_ick_3430es2";
67 clocks = <&core_l3_ick>;
68 };
69
70 ssi_ick: clock-ssi-ick-3430es2@0 {
71 reg = <0>;
72 #clock-cells = <0>;
73 compatible = "ti,omap3-ssi-interface-clock";
74 clock-output-names = "ssi_ick_3430es2";
75 clocks = <&ssi_l4_ick>;
76 };
77 };
78
79 ssi_l4_ick: ssi_l4_ick {
80 #clock-cells = <0>;
81 compatible = "fixed-factor-clock";
82 clocks = <&l4_ick>;
83 clock-mult = <1>;
84 clock-div = <1>;
85 };
86
87 clock@c00 {
88 compatible = "ti,clksel";
89 reg = <0xc00>;
90 #clock-cells = <2>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 usim_gate_fck: clock-usim-gate-fck@9 {
95 reg = <9>;
96 #clock-cells = <0>;
97 compatible = "ti,composite-gate-clock";
98 clock-output-names = "usim_gate_fck";
99 clocks = <&omap_96m_fck>;
100 };
101 };
102
103 sys_d2_ck: sys_d2_ck {
104 #clock-cells = <0>;
105 compatible = "fixed-factor-clock";
106 clocks = <&sys_ck>;
107 clock-mult = <1>;
108 clock-div = <2>;
109 };
110
111 omap_96m_d2_fck: omap_96m_d2_fck {
112 #clock-cells = <0>;
113 compatible = "fixed-factor-clock";
114 clocks = <&omap_96m_fck>;
115 clock-mult = <1>;
116 clock-div = <2>;
117 };
118
119 omap_96m_d4_fck: omap_96m_d4_fck {
120 #clock-cells = <0>;
121 compatible = "fixed-factor-clock";
122 clocks = <&omap_96m_fck>;
123 clock-mult = <1>;
124 clock-div = <4>;
125 };
126
127 omap_96m_d8_fck: omap_96m_d8_fck {
128 #clock-cells = <0>;
129 compatible = "fixed-factor-clock";
130 clocks = <&omap_96m_fck>;
131 clock-mult = <1>;
132 clock-div = <8>;
133 };
134
135 omap_96m_d10_fck: omap_96m_d10_fck {
136 #clock-cells = <0>;
137 compatible = "fixed-factor-clock";
138 clocks = <&omap_96m_fck>;
139 clock-mult = <1>;
140 clock-div = <10>;
141 };
142
143 dpll5_m2_d4_ck: dpll5_m2_d4_ck {
144 #clock-cells = <0>;
145 compatible = "fixed-factor-clock";
146 clocks = <&dpll5_m2_ck>;
147 clock-mult = <1>;
148 clock-div = <4>;
149 };
150
151 dpll5_m2_d8_ck: dpll5_m2_d8_ck {
152 #clock-cells = <0>;
153 compatible = "fixed-factor-clock";
154 clocks = <&dpll5_m2_ck>;
155 clock-mult = <1>;
156 clock-div = <8>;
157 };
158
159 dpll5_m2_d16_ck: dpll5_m2_d16_ck {
160 #clock-cells = <0>;
161 compatible = "fixed-factor-clock";
162 clocks = <&dpll5_m2_ck>;
163 clock-mult = <1>;
164 clock-div = <16>;
165 };
166
167 dpll5_m2_d20_ck: dpll5_m2_d20_ck {
168 #clock-cells = <0>;
169 compatible = "fixed-factor-clock";
170 clocks = <&dpll5_m2_ck>;
171 clock-mult = <1>;
172 clock-div = <20>;
173 };
174
175 clock@c40 {
176 compatible = "ti,clksel";
177 reg = <0xc40>;
178 #clock-cells = <2>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181
182 usim_mux_fck: clock-usim-mux-fck@3 {
183 reg = <3>;
184 #clock-cells = <0>;
185 compatible = "ti,composite-mux-clock";
186 clock-output-names = "usim_mux_fck";
187 clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
188 ti,index-starts-at-one;
189 };
190 };
191
192 usim_fck: usim_fck {
193 #clock-cells = <0>;
194 compatible = "ti,composite-clock";
195 clocks = <&usim_gate_fck>, <&usim_mux_fck>;
196 };
197
198 clock@c10 {
199 compatible = "ti,clksel";
200 reg = <0xc10>;
201 #clock-cells = <2>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204
205 usim_ick: clock-usim-ick@9 {
206 reg = <9>;
207 #clock-cells = <0>;
208 compatible = "ti,omap3-interface-clock";
209 clock-output-names = "usim_ick";
210 clocks = <&wkup_l4_ick>;
211 };
212 };
213 };
214
215 &cm_clockdomains {
216 core_l3_clkdm: core_l3_clkdm {
217 compatible = "ti,clockdomain";
218 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
219 };
220
221 wkup_clkdm: wkup_clkdm {
222 compatible = "ti,clockdomain";
223 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
224 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
225 <&gpt1_ick>, <&usim_ick>;
226 };
227
228 core_l4_clkdm: core_l4_clkdm {
229 compatible = "ti,clockdomain";
230 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
231 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
232 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
233 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
234 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
235 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
236 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
237 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
238 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
239 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
240 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
241 <&ssi_ick>;
242 };
243 };
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