1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Device Tree Source for OMAP3 clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7 &prm_clocks {
8 virt_16_8m_ck: virt_16_8m_ck {
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
12 };
13
14 osc_sys_ck: osc_sys_ck@d40 {
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
17 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
18 reg = <0x0d40>;
19 };
20
21 sys_ck: sys_ck@1270 {
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
24 clocks = <&osc_sys_ck>;
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
27 reg = <0x1270>;
28 ti,index-starts-at-one;
29 };
30
31 sys_clkout1: sys_clkout1@d70 {
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
34 clocks = <&osc_sys_ck>;
35 reg = <0x0d70>;
36 ti,bit-shift = <7>;
37 };
38
39 dpll3_x2_ck: dpll3_x2_ck {
40 #clock-cells = <0>;
41 compatible = "fixed-factor-clock";
42 clocks = <&dpll3_ck>;
43 clock-mult = <2>;
44 clock-div = <1>;
45 };
46
47 dpll3_m2x2_ck: dpll3_m2x2_ck {
48 #clock-cells = <0>;
49 compatible = "fixed-factor-clock";
50 clocks = <&dpll3_m2_ck>;
51 clock-mult = <2>;
52 clock-div = <1>;
53 };
54
55 dpll4_x2_ck: dpll4_x2_ck {
56 #clock-cells = <0>;
57 compatible = "fixed-factor-clock";
58 clocks = <&dpll4_ck>;
59 clock-mult = <2>;
60 clock-div = <1>;
61 };
62
63 corex2_fck: corex2_fck {
64 #clock-cells = <0>;
65 compatible = "fixed-factor-clock";
66 clocks = <&dpll3_m2x2_ck>;
67 clock-mult = <1>;
68 clock-div = <1>;
69 };
70
71 wkup_l4_ick: wkup_l4_ick {
72 #clock-cells = <0>;
73 compatible = "fixed-factor-clock";
74 clocks = <&sys_ck>;
75 clock-mult = <1>;
76 clock-div = <1>;
77 };
78 };
79
80 &scm_clocks {
81 /* CONTROL_DEVCONF1 */
82 clock@68 {
83 compatible = "ti,clksel";
84 reg = <0x68>;
85 #clock-cells = <2>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 mcbsp5_mux_fck: clock-mcbsp5-mux-fck@4 {
90 reg = <4>;
91 #clock-cells = <0>;
92 compatible = "ti,composite-mux-clock";
93 clock-output-names = "mcbsp5_mux_fck";
94 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 };
96
97 mcbsp3_mux_fck: clock-mcbsp3-mux-fck@0 {
98 reg = <0>;
99 #clock-cells = <0>;
100 compatible = "ti,composite-mux-clock";
101 clock-output-names = "mcbsp3_mux_fck";
102 clocks = <&per_96m_fck>, <&mcbsp_clks>;
103 };
104
105 mcbsp4_mux_fck: clock-mcbsp4-mux-fck@2 {
106 reg = <2>;
107 #clock-cells = <0>;
108 compatible = "ti,composite-mux-clock";
109 clock-output-names = "mcbsp4_mux_fck";
110 clocks = <&per_96m_fck>, <&mcbsp_clks>;
111 };
112 };
113
114 mcbsp5_fck: mcbsp5_fck {
115 #clock-cells = <0>;
116 compatible = "ti,composite-clock";
117 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
118 };
119
120 /* CONTROL_DEVCONF0 */
121 clock@4 {
122 compatible = "ti,clksel";
123 reg = <0x4>;
124 #clock-cells = <2>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 mcbsp1_mux_fck: clock-mcbsp1-mux-fck@2 {
129 reg = <2>;
130 #clock-cells = <0>;
131 compatible = "ti,composite-mux-clock";
132 clock-output-names = "mcbsp1_mux_fck";
133 clocks = <&core_96m_fck>, <&mcbsp_clks>;
134 };
135
136 mcbsp2_mux_fck: clock-mcbsp2-mux-fck@6 {
137 reg = <6>;
138 #clock-cells = <0>;
139 compatible = "ti,composite-mux-clock";
140 clock-output-names = "mcbsp2_mux_fck";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>;
142 };
143 };
144
145 mcbsp1_fck: mcbsp1_fck {
146 #clock-cells = <0>;
147 compatible = "ti,composite-clock";
148 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
149 };
150
151 mcbsp2_fck: mcbsp2_fck {
152 #clock-cells = <0>;
153 compatible = "ti,composite-clock";
154 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
155 };
156
157 mcbsp3_fck: mcbsp3_fck {
158 #clock-cells = <0>;
159 compatible = "ti,composite-clock";
160 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
161 };
162
163 mcbsp4_fck: mcbsp4_fck {
164 #clock-cells = <0>;
165 compatible = "ti,composite-clock";
166 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
167 };
168 };
169 &cm_clocks {
170 dummy_apb_pclk: dummy_apb_pclk {
171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <0x0>;
174 };
175
176 omap_32k_fck: omap_32k_fck {
177 #clock-cells = <0>;
178 compatible = "fixed-clock";
179 clock-frequency = <32768>;
180 };
181
182 virt_12m_ck: virt_12m_ck {
183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-frequency = <12000000>;
186 };
187
188 virt_13m_ck: virt_13m_ck {
189 #clock-cells = <0>;
190 compatible = "fixed-clock";
191 clock-frequency = <13000000>;
192 };
193
194 virt_19200000_ck: virt_19200000_ck {
195 #clock-cells = <0>;
196 compatible = "fixed-clock";
197 clock-frequency = <19200000>;
198 };
199
200 virt_26000000_ck: virt_26000000_ck {
201 #clock-cells = <0>;
202 compatible = "fixed-clock";
203 clock-frequency = <26000000>;
204 };
205
206 virt_38_4m_ck: virt_38_4m_ck {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-frequency = <38400000>;
210 };
211
212 dpll4_ck: dpll4_ck@d00 {
213 #clock-cells = <0>;
214 compatible = "ti,omap3-dpll-per-clock";
215 clocks = <&sys_ck>, <&sys_ck>;
216 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
217 };
218
219 dpll4_m2_ck: dpll4_m2_ck@d48 {
220 #clock-cells = <0>;
221 compatible = "ti,divider-clock";
222 clocks = <&dpll4_ck>;
223 ti,max-div = <63>;
224 reg = <0x0d48>;
225 ti,index-starts-at-one;
226 };
227
228 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
229 #clock-cells = <0>;
230 compatible = "fixed-factor-clock";
231 clocks = <&dpll4_m2_ck>;
232 clock-mult = <2>;
233 clock-div = <1>;
234 };
235
236 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
237 #clock-cells = <0>;
238 compatible = "ti,gate-clock";
239 clocks = <&dpll4_m2x2_mul_ck>;
240 ti,bit-shift = <0x1b>;
241 reg = <0x0d00>;
242 ti,set-bit-to-disable;
243 };
244
245 omap_96m_alwon_fck: omap_96m_alwon_fck {
246 #clock-cells = <0>;
247 compatible = "fixed-factor-clock";
248 clocks = <&dpll4_m2x2_ck>;
249 clock-mult = <1>;
250 clock-div = <1>;
251 };
252
253 dpll3_ck: dpll3_ck@d00 {
254 #clock-cells = <0>;
255 compatible = "ti,omap3-dpll-core-clock";
256 clocks = <&sys_ck>, <&sys_ck>;
257 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
258 };
259
260 /* CM_CLKSEL1_EMU */
261 clock@1140 {
262 compatible = "ti,clksel";
263 reg = <0x1140>;
264 #clock-cells = <2>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267
268 dpll3_m3_ck: clock-dpll3-m3@16 {
269 reg = <16>;
270 #clock-cells = <0>;
271 compatible = "ti,divider-clock";
272 clock-output-names = "dpll3_m3_ck";
273 clocks = <&dpll3_ck>;
274 ti,max-div = <31>;
275 ti,index-starts-at-one;
276 };
277
278 dpll4_m6_ck: clock-dpll4-m6@24 {
279 reg = <24>;
280 #clock-cells = <0>;
281 compatible = "ti,divider-clock";
282 clock-output-names = "dpll4_m6_ck";
283 clocks = <&dpll4_ck>;
284 ti,max-div = <63>;
285 ti,index-starts-at-one;
286 };
287
288 emu_src_mux_ck: clock-emu-src-mux@0 {
289 reg = <0>;
290 #clock-cells = <0>;
291 compatible = "ti,mux-clock";
292 clock-output-names = "emu_src_mux_ck";
293 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
294 };
295
296 pclk_fck: clock-pclk-fck@8 {
297 reg = <8>;
298 #clock-cells = <0>;
299 compatible = "ti,divider-clock";
300 clock-output-names = "pclk_fck";
301 clocks = <&emu_src_ck>;
302 ti,max-div = <7>;
303 ti,index-starts-at-one;
304 };
305
306 pclkx2_fck: clock-pclkx2-fck@6 {
307 reg = <6>;
308 #clock-cells = <0>;
309 compatible = "ti,divider-clock";
310 clock-output-names = "pclkx2_fck";
311 clocks = <&emu_src_ck>;
312 ti,max-div = <3>;
313 ti,index-starts-at-one;
314 };
315
316 atclk_fck: clock-atclk-fck@4 {
317 reg = <4>;
318 #clock-cells = <0>;
319 compatible = "ti,divider-clock";
320 clock-output-names = "atclk_fck";
321 clocks = <&emu_src_ck>;
322 ti,max-div = <3>;
323 ti,index-starts-at-one;
324 };
325
326 traceclk_src_fck: clock-traceclk-src-fck@2 {
327 reg = <2>;
328 #clock-cells = <0>;
329 compatible = "ti,mux-clock";
330 clock-output-names = "traceclk_src_fck";
331 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
332 };
333
334 traceclk_fck: clock-traceclk-fck@11 {
335 reg = <11>;
336 #clock-cells = <0>;
337 compatible = "ti,divider-clock";
338 clock-output-names = "traceclk_fck";
339 clocks = <&traceclk_src_fck>;
340 ti,max-div = <7>;
341 ti,index-starts-at-one;
342 };
343 };
344
345 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
346 #clock-cells = <0>;
347 compatible = "fixed-factor-clock";
348 clocks = <&dpll3_m3_ck>;
349 clock-mult = <2>;
350 clock-div = <1>;
351 };
352
353 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
354 #clock-cells = <0>;
355 compatible = "ti,gate-clock";
356 clocks = <&dpll3_m3x2_mul_ck>;
357 ti,bit-shift = <0xc>;
358 reg = <0x0d00>;
359 ti,set-bit-to-disable;
360 };
361
362 emu_core_alwon_ck: emu_core_alwon_ck {
363 #clock-cells = <0>;
364 compatible = "fixed-factor-clock";
365 clocks = <&dpll3_m3x2_ck>;
366 clock-mult = <1>;
367 clock-div = <1>;
368 };
369
370 sys_altclk: sys_altclk {
371 #clock-cells = <0>;
372 compatible = "fixed-clock";
373 clock-frequency = <0x0>;
374 };
375
376 mcbsp_clks: mcbsp_clks {
377 #clock-cells = <0>;
378 compatible = "fixed-clock";
379 clock-frequency = <0x0>;
380 };
381
382 core_ck: core_ck {
383 #clock-cells = <0>;
384 compatible = "fixed-factor-clock";
385 clocks = <&dpll3_m2_ck>;
386 clock-mult = <1>;
387 clock-div = <1>;
388 };
389
390 dpll1_fck: dpll1_fck@940 {
391 #clock-cells = <0>;
392 compatible = "ti,divider-clock";
393 clocks = <&core_ck>;
394 ti,bit-shift = <19>;
395 ti,max-div = <7>;
396 reg = <0x0940>;
397 ti,index-starts-at-one;
398 };
399
400 dpll1_ck: dpll1_ck@904 {
401 #clock-cells = <0>;
402 compatible = "ti,omap3-dpll-clock";
403 clocks = <&sys_ck>, <&dpll1_fck>;
404 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
405 };
406
407 dpll1_x2_ck: dpll1_x2_ck {
408 #clock-cells = <0>;
409 compatible = "fixed-factor-clock";
410 clocks = <&dpll1_ck>;
411 clock-mult = <2>;
412 clock-div = <1>;
413 };
414
415 dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
416 #clock-cells = <0>;
417 compatible = "ti,divider-clock";
418 clocks = <&dpll1_x2_ck>;
419 ti,max-div = <31>;
420 reg = <0x0944>;
421 ti,index-starts-at-one;
422 };
423
424 cm_96m_fck: cm_96m_fck {
425 #clock-cells = <0>;
426 compatible = "fixed-factor-clock";
427 clocks = <&omap_96m_alwon_fck>;
428 clock-mult = <1>;
429 clock-div = <1>;
430 };
431
432 /* CM_CLKSEL1_PLL */
433 clock@d40 {
434 compatible = "ti,clksel";
435 reg = <0xd40>;
436 #clock-cells = <2>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 dpll3_m2_ck: clock-dpll3-m2@27 {
441 reg = <27>;
442 #clock-cells = <0>;
443 compatible = "ti,divider-clock";
444 clock-output-names = "dpll3_m2_ck";
445 clocks = <&dpll3_ck>;
446 ti,max-div = <31>;
447 ti,index-starts-at-one;
448 };
449
450 omap_96m_fck: clock-omap-96m-fck@6 {
451 reg = <6>;
452 #clock-cells = <0>;
453 compatible = "ti,mux-clock";
454 clock-output-names = "omap_96m_fck";
455 clocks = <&cm_96m_fck>, <&sys_ck>;
456 };
457
458 omap_54m_fck: clock-omap-54m-fck@5 {
459 reg = <5>;
460 #clock-cells = <0>;
461 compatible = "ti,mux-clock";
462 clock-output-names = "omap_54m_fck";
463 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
464 };
465
466 omap_48m_fck: clock-omap-48m-fck@3 {
467 reg = <3>;
468 #clock-cells = <0>;
469 compatible = "ti,mux-clock";
470 clock-output-names = "omap_48m_fck";
471 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
472 };
473 };
474
475 /* CM_CLKSEL_DSS */
476 clock@e40 {
477 compatible = "ti,clksel";
478 reg = <0xe40>;
479 #clock-cells = <2>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482
483 dpll4_m3_ck: clock-dpll4-m3@8 {
484 reg = <8>;
485 #clock-cells = <0>;
486 compatible = "ti,divider-clock";
487 clock-output-names = "dpll4_m3_ck";
488 clocks = <&dpll4_ck>;
489 ti,max-div = <32>;
490 ti,index-starts-at-one;
491 };
492
493 dpll4_m4_ck: clock-dpll4-m4@0 {
494 reg = <0>;
495 #clock-cells = <0>;
496 compatible = "ti,divider-clock";
497 clock-output-names = "dpll4_m4_ck";
498 clocks = <&dpll4_ck>;
499 ti,max-div = <16>;
500 ti,index-starts-at-one;
501 };
502 };
503
504 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
505 #clock-cells = <0>;
506 compatible = "fixed-factor-clock";
507 clocks = <&dpll4_m3_ck>;
508 clock-mult = <2>;
509 clock-div = <1>;
510 };
511
512 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
513 #clock-cells = <0>;
514 compatible = "ti,gate-clock";
515 clocks = <&dpll4_m3x2_mul_ck>;
516 ti,bit-shift = <0x1c>;
517 reg = <0x0d00>;
518 ti,set-bit-to-disable;
519 };
520
521 cm_96m_d2_fck: cm_96m_d2_fck {
522 #clock-cells = <0>;
523 compatible = "fixed-factor-clock";
524 clocks = <&cm_96m_fck>;
525 clock-mult = <1>;
526 clock-div = <2>;
527 };
528
529 omap_12m_fck: omap_12m_fck {
530 #clock-cells = <0>;
531 compatible = "fixed-factor-clock";
532 clocks = <&omap_48m_fck>;
533 clock-mult = <1>;
534 clock-div = <4>;
535 };
536
537 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
538 #clock-cells = <0>;
539 compatible = "ti,fixed-factor-clock";
540 clocks = <&dpll4_m4_ck>;
541 ti,clock-mult = <2>;
542 ti,clock-div = <1>;
543 ti,set-rate-parent;
544 };
545
546 dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
547 #clock-cells = <0>;
548 compatible = "ti,gate-clock";
549 clocks = <&dpll4_m4x2_mul_ck>;
550 ti,bit-shift = <0x1d>;
551 reg = <0x0d00>;
552 ti,set-bit-to-disable;
553 ti,set-rate-parent;
554 };
555
556 dpll4_m5_ck: dpll4_m5_ck@f40 {
557 #clock-cells = <0>;
558 compatible = "ti,divider-clock";
559 clocks = <&dpll4_ck>;
560 ti,max-div = <63>;
561 reg = <0x0f40>;
562 ti,index-starts-at-one;
563 };
564
565 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
566 #clock-cells = <0>;
567 compatible = "ti,fixed-factor-clock";
568 clocks = <&dpll4_m5_ck>;
569 ti,clock-mult = <2>;
570 ti,clock-div = <1>;
571 ti,set-rate-parent;
572 };
573
574 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
575 #clock-cells = <0>;
576 compatible = "ti,gate-clock";
577 clocks = <&dpll4_m5x2_mul_ck>;
578 ti,bit-shift = <0x1e>;
579 reg = <0x0d00>;
580 ti,set-bit-to-disable;
581 ti,set-rate-parent;
582 };
583
584 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
585 #clock-cells = <0>;
586 compatible = "fixed-factor-clock";
587 clocks = <&dpll4_m6_ck>;
588 clock-mult = <2>;
589 clock-div = <1>;
590 };
591
592 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
593 #clock-cells = <0>;
594 compatible = "ti,gate-clock";
595 clocks = <&dpll4_m6x2_mul_ck>;
596 ti,bit-shift = <0x1f>;
597 reg = <0x0d00>;
598 ti,set-bit-to-disable;
599 };
600
601 emu_per_alwon_ck: emu_per_alwon_ck {
602 #clock-cells = <0>;
603 compatible = "fixed-factor-clock";
604 clocks = <&dpll4_m6x2_ck>;
605 clock-mult = <1>;
606 clock-div = <1>;
607 };
608
609 /* CM_CLKOUT_CTRL */
610 clock@d70 {
611 compatible = "ti,clksel";
612 reg = <0xd70>;
613 #clock-cells = <2>;
614 #address-cells = <1>;
615 #size-cells = <0>;
616
617 clkout2_src_gate_ck: clock-clkout2-src-gate@7 {
618 reg = <7>;
619 #clock-cells = <0>;
620 compatible = "ti,composite-no-wait-gate-clock";
621 clock-output-names = "clkout2_src_gate_ck";
622 clocks = <&core_ck>;
623 };
624
625 clkout2_src_mux_ck: clock-clkout2-src-mux@0 {
626 reg = <0>;
627 #clock-cells = <0>;
628 compatible = "ti,composite-mux-clock";
629 clock-output-names = "clkout2_src_mux_ck";
630 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
631 };
632
633 sys_clkout2: clock-sys-clkout2@3 {
634 reg = <3>;
635 #clock-cells = <0>;
636 compatible = "ti,divider-clock";
637 clock-output-names = "sys_clkout2";
638 clocks = <&clkout2_src_ck>;
639 ti,max-div = <64>;
640 ti,index-power-of-two;
641 };
642 };
643
644 clkout2_src_ck: clkout2_src_ck {
645 #clock-cells = <0>;
646 compatible = "ti,composite-clock";
647 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
648 };
649
650 mpu_ck: mpu_ck {
651 #clock-cells = <0>;
652 compatible = "fixed-factor-clock";
653 clocks = <&dpll1_x2m2_ck>;
654 clock-mult = <1>;
655 clock-div = <1>;
656 };
657
658 arm_fck: arm_fck@924 {
659 #clock-cells = <0>;
660 compatible = "ti,divider-clock";
661 clocks = <&mpu_ck>;
662 reg = <0x0924>;
663 ti,max-div = <2>;
664 };
665
666 emu_mpu_alwon_ck: emu_mpu_alwon_ck {
667 #clock-cells = <0>;
668 compatible = "fixed-factor-clock";
669 clocks = <&mpu_ck>;
670 clock-mult = <1>;
671 clock-div = <1>;
672 };
673
674 /* CM_CLKSEL_CORE */
675 clock@a40 {
676 compatible = "ti,clksel";
677 reg = <0xa40>;
678 #clock-cells = <2>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 l3_ick: clock-l3-ick@0 {
683 reg = <0>;
684 #clock-cells = <0>;
685 compatible = "ti,divider-clock";
686 clock-output-names = "l3_ick";
687 clocks = <&core_ck>;
688 ti,max-div = <3>;
689 ti,index-starts-at-one;
690 };
691
692 l4_ick: clock-l4-ick@2 {
693 reg = <2>;
694 #clock-cells = <0>;
695 compatible = "ti,divider-clock";
696 clock-output-names = "l4_ick";
697 clocks = <&l3_ick>;
698 ti,max-div = <3>;
699 ti,index-starts-at-one;
700 };
701
702 gpt10_mux_fck: clock-gpt10-mux-fck@6 {
703 reg = <6>;
704 #clock-cells = <0>;
705 compatible = "ti,composite-mux-clock";
706 clock-output-names = "gpt10_mux_fck";
707 clocks = <&omap_32k_fck>, <&sys_ck>;
708 };
709
710 gpt11_mux_fck: clock-gpt11-mux-fck@7 {
711 reg = <7>;
712 #clock-cells = <0>;
713 compatible = "ti,composite-mux-clock";
714 clock-output-names = "gpt11_mux_fck";
715 clocks = <&omap_32k_fck>, <&sys_ck>;
716 };
717 };
718
719 /* CM_CLKSEL_WKUP */
720 clock@c40 {
721 compatible = "ti,clksel";
722 reg = <0xc40>;
723 #clock-cells = <2>;
724 #address-cells = <1>;
725 #size-cells = <0>;
726
727 rm_ick: clock-rm-ick@1 {
728 reg = <1>;
729 #clock-cells = <0>;
730 compatible = "ti,divider-clock";
731 clock-output-names = "rm_ick";
732 clocks = <&l4_ick>;
733 ti,max-div = <3>;
734 ti,index-starts-at-one;
735 };
736
737 gpt1_mux_fck: clock-gpt1-mux-fck@0 {
738 reg = <0>;
739 #clock-cells = <0>;
740 compatible = "ti,composite-mux-clock";
741 clock-output-names = "gpt1_mux_fck";
742 clocks = <&omap_32k_fck>, <&sys_ck>;
743 };
744 };
745
746 /* CM_FCLKEN1_CORE */
747 clock@a00 {
748 compatible = "ti,clksel";
749 reg = <0xa00>;
750 #clock-cells = <2>;
751 #address-cells = <1>;
752 #size-cells = <0>;
753
754 gpt10_gate_fck: clock-gpt10-gate-fck@11 {
755 reg = <11>;
756 #clock-cells = <0>;
757 compatible = "ti,composite-gate-clock";
758 clock-output-names = "gpt10_gate_fck";
759 clocks = <&sys_ck>;
760 };
761
762 gpt11_gate_fck: clock-gpt11-gate-fck@12 {
763 reg = <12>;
764 #clock-cells = <0>;
765 compatible = "ti,composite-gate-clock";
766 clock-output-names = "gpt11_gate_fck";
767 clocks = <&sys_ck>;
768 };
769
770 mmchs2_fck: clock-mmchs2-fck@25 {
771 reg = <25>;
772 #clock-cells = <0>;
773 compatible = "ti,wait-gate-clock";
774 clock-output-names = "mmchs2_fck";
775 clocks = <&core_96m_fck>;
776 };
777
778 mmchs1_fck: clock-mmchs1-fck@24 {
779 reg = <24>;
780 #clock-cells = <0>;
781 compatible = "ti,wait-gate-clock";
782 clock-output-names = "mmchs1_fck";
783 clocks = <&core_96m_fck>;
784 };
785
786 i2c3_fck: clock-i2c3-fck@17 {
787 reg = <17>;
788 #clock-cells = <0>;
789 compatible = "ti,wait-gate-clock";
790 clock-output-names = "i2c3_fck";
791 clocks = <&core_96m_fck>;
792 };
793
794 i2c2_fck: clock-i2c2-fck@16 {
795 reg = <16>;
796 #clock-cells = <0>;
797 compatible = "ti,wait-gate-clock";
798 clock-output-names = "i2c2_fck";
799 clocks = <&core_96m_fck>;
800 };
801
802 i2c1_fck: clock-i2c1-fck@15 {
803 reg = <15>;
804 #clock-cells = <0>;
805 compatible = "ti,wait-gate-clock";
806 clock-output-names = "i2c1_fck";
807 clocks = <&core_96m_fck>;
808 };
809
810 mcbsp5_gate_fck: clock-mcbsp5-gate-fck@10 {
811 reg = <10>;
812 #clock-cells = <0>;
813 compatible = "ti,composite-gate-clock";
814 clock-output-names = "mcbsp5_gate_fck";
815 clocks = <&mcbsp_clks>;
816 };
817
818 mcbsp1_gate_fck: clock-mcbsp1-gate-fck@9 {
819 reg = <9>;
820 #clock-cells = <0>;
821 compatible = "ti,composite-gate-clock";
822 clock-output-names = "mcbsp1_gate_fck";
823 clocks = <&mcbsp_clks>;
824 };
825
826 mcspi4_fck: clock-mcspi4-fck@21 {
827 reg = <21>;
828 #clock-cells = <0>;
829 compatible = "ti,wait-gate-clock";
830 clock-output-names = "mcspi4_fck";
831 clocks = <&core_48m_fck>;
832 };
833
834 mcspi3_fck: clock-mcspi3-fck@20 {
835 reg = <20>;
836 #clock-cells = <0>;
837 compatible = "ti,wait-gate-clock";
838 clock-output-names = "mcspi3_fck";
839 clocks = <&core_48m_fck>;
840 };
841
842 mcspi2_fck: clock-mcspi2-fck@19 {
843 reg = <19>;
844 #clock-cells = <0>;
845 compatible = "ti,wait-gate-clock";
846 clock-output-names = "mcspi2_fck";
847 clocks = <&core_48m_fck>;
848 };
849
850 mcspi1_fck: clock-mcspi1-fck@18 {
851 reg = <18>;
852 #clock-cells = <0>;
853 compatible = "ti,wait-gate-clock";
854 clock-output-names = "mcspi1_fck";
855 clocks = <&core_48m_fck>;
856 };
857
858 uart2_fck: clock-uart2-fck@14 {
859 reg = <14>;
860 #clock-cells = <0>;
861 compatible = "ti,wait-gate-clock";
862 clock-output-names = "uart2_fck";
863 clocks = <&core_48m_fck>;
864 };
865
866 uart1_fck: clock-uart1-fck@13 {
867 reg = <13>;
868 #clock-cells = <0>;
869 compatible = "ti,wait-gate-clock";
870 clock-output-names = "uart1_fck";
871 clocks = <&core_48m_fck>;
872 };
873
874 hdq_fck: clock-hdq-fck@22 {
875 reg = <22>;
876 #clock-cells = <0>;
877 compatible = "ti,wait-gate-clock";
878 clock-output-names = "hdq_fck";
879 clocks = <&core_12m_fck>;
880 };
881 };
882
883 gpt10_fck: gpt10_fck {
884 #clock-cells = <0>;
885 compatible = "ti,composite-clock";
886 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
887 };
888
889 gpt11_fck: gpt11_fck {
890 #clock-cells = <0>;
891 compatible = "ti,composite-clock";
892 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
893 };
894
895 core_96m_fck: core_96m_fck {
896 #clock-cells = <0>;
897 compatible = "fixed-factor-clock";
898 clocks = <&omap_96m_fck>;
899 clock-mult = <1>;
900 clock-div = <1>;
901 };
902
903 core_48m_fck: core_48m_fck {
904 #clock-cells = <0>;
905 compatible = "fixed-factor-clock";
906 clocks = <&omap_48m_fck>;
907 clock-mult = <1>;
908 clock-div = <1>;
909 };
910
911 core_12m_fck: core_12m_fck {
912 #clock-cells = <0>;
913 compatible = "fixed-factor-clock";
914 clocks = <&omap_12m_fck>;
915 clock-mult = <1>;
916 clock-div = <1>;
917 };
918
919 core_l3_ick: core_l3_ick {
920 #clock-cells = <0>;
921 compatible = "fixed-factor-clock";
922 clocks = <&l3_ick>;
923 clock-mult = <1>;
924 clock-div = <1>;
925 };
926
927 /* CM_ICLKEN1_CORE */
928 clock@a10 {
929 compatible = "ti,clksel";
930 reg = <0xa10>;
931 #clock-cells = <2>;
932 #address-cells = <1>;
933 #size-cells = <0>;
934
935 sdrc_ick: clock-sdrc-ick@1 {
936 reg = <1>;
937 #clock-cells = <0>;
938 compatible = "ti,wait-gate-clock";
939 clock-output-names = "sdrc_ick";
940 clocks = <&core_l3_ick>;
941 };
942
943 mmchs2_ick: clock-mmchs2-ick@25 {
944 reg = <25>;
945 #clock-cells = <0>;
946 compatible = "ti,omap3-interface-clock";
947 clock-output-names = "mmchs2_ick";
948 clocks = <&core_l4_ick>;
949 };
950
951 mmchs1_ick: clock-mmchs1-ick@24 {
952 reg = <24>;
953 #clock-cells = <0>;
954 compatible = "ti,omap3-interface-clock";
955 clock-output-names = "mmchs1_ick";
956 clocks = <&core_l4_ick>;
957 };
958
959 hdq_ick: clock-hdq-ick@22 {
960 reg = <22>;
961 #clock-cells = <0>;
962 compatible = "ti,omap3-interface-clock";
963 clock-output-names = "hdq_ick";
964 clocks = <&core_l4_ick>;
965 };
966
967 mcspi4_ick: clock-mcspi4-ick@21 {
968 reg = <21>;
969 #clock-cells = <0>;
970 compatible = "ti,omap3-interface-clock";
971 clock-output-names = "mcspi4_ick";
972 clocks = <&core_l4_ick>;
973 };
974
975 mcspi3_ick: clock-mcspi3-ick@20 {
976 reg = <20>;
977 #clock-cells = <0>;
978 compatible = "ti,omap3-interface-clock";
979 clock-output-names = "mcspi3_ick";
980 clocks = <&core_l4_ick>;
981 };
982
983 mcspi2_ick: clock-mcspi2-ick@19 {
984 reg = <19>;
985 #clock-cells = <0>;
986 compatible = "ti,omap3-interface-clock";
987 clock-output-names = "mcspi2_ick";
988 clocks = <&core_l4_ick>;
989 };
990
991 mcspi1_ick: clock-mcspi1-ick@18 {
992 reg = <18>;
993 #clock-cells = <0>;
994 compatible = "ti,omap3-interface-clock";
995 clock-output-names = "mcspi1_ick";
996 clocks = <&core_l4_ick>;
997 };
998
999 i2c3_ick: clock-i2c3-ick@17 {
1000 reg = <17>;
1001 #clock-cells = <0>;
1002 compatible = "ti,omap3-interface-clock";
1003 clock-output-names = "i2c3_ick";
1004 clocks = <&core_l4_ick>;
1005 };
1006
1007 i2c2_ick: clock-i2c2-ick@16 {
1008 reg = <16>;
1009 #clock-cells = <0>;
1010 compatible = "ti,omap3-interface-clock";
1011 clock-output-names = "i2c2_ick";
1012 clocks = <&core_l4_ick>;
1013 };
1014
1015 i2c1_ick: clock-i2c1-ick@15 {
1016 reg = <15>;
1017 #clock-cells = <0>;
1018 compatible = "ti,omap3-interface-clock";
1019 clock-output-names = "i2c1_ick";
1020 clocks = <&core_l4_ick>;
1021 };
1022
1023 uart2_ick: clock-uart2-ick@14 {
1024 reg = <14>;
1025 #clock-cells = <0>;
1026 compatible = "ti,omap3-interface-clock";
1027 clock-output-names = "uart2_ick";
1028 clocks = <&core_l4_ick>;
1029 };
1030
1031 uart1_ick: clock-uart1-ick@13 {
1032 reg = <13>;
1033 #clock-cells = <0>;
1034 compatible = "ti,omap3-interface-clock";
1035 clock-output-names = "uart1_ick";
1036 clocks = <&core_l4_ick>;
1037 };
1038
1039 gpt11_ick: clock-gpt11-ick@12 {
1040 reg = <12>;
1041 #clock-cells = <0>;
1042 compatible = "ti,omap3-interface-clock";
1043 clock-output-names = "gpt11_ick";
1044 clocks = <&core_l4_ick>;
1045 };
1046
1047 gpt10_ick: clock-gpt10-ick@11 {
1048 reg = <11>;
1049 #clock-cells = <0>;
1050 compatible = "ti,omap3-interface-clock";
1051 clock-output-names = "gpt10_ick";
1052 clocks = <&core_l4_ick>;
1053 };
1054
1055 mcbsp5_ick: clock-mcbsp5-ick@10 {
1056 reg = <10>;
1057 #clock-cells = <0>;
1058 compatible = "ti,omap3-interface-clock";
1059 clock-output-names = "mcbsp5_ick";
1060 clocks = <&core_l4_ick>;
1061 };
1062
1063 mcbsp1_ick: clock-mcbsp1-ick@9 {
1064 reg = <9>;
1065 #clock-cells = <0>;
1066 compatible = "ti,omap3-interface-clock";
1067 clock-output-names = "mcbsp1_ick";
1068 clocks = <&core_l4_ick>;
1069 };
1070
1071 omapctrl_ick: clock-omapctrl-ick@6 {
1072 reg = <6>;
1073 #clock-cells = <0>;
1074 compatible = "ti,omap3-interface-clock";
1075 clock-output-names = "omapctrl_ick";
1076 clocks = <&core_l4_ick>;
1077 };
1078
1079 aes2_ick: clock-aes2-ick@28 {
1080 reg = <28>;
1081 #clock-cells = <0>;
1082 compatible = "ti,omap3-interface-clock";
1083 clock-output-names = "aes2_ick";
1084 clocks = <&core_l4_ick>;
1085 };
1086
1087 sha12_ick: clock-sha12-ick@27 {
1088 reg = <27>;
1089 #clock-cells = <0>;
1090 compatible = "ti,omap3-interface-clock";
1091 clock-output-names = "sha12_ick";
1092 clocks = <&core_l4_ick>;
1093 };
1094 };
1095
1096 gpmc_fck: gpmc_fck {
1097 #clock-cells = <0>;
1098 compatible = "fixed-factor-clock";
1099 clocks = <&core_l3_ick>;
1100 clock-mult = <1>;
1101 clock-div = <1>;
1102 };
1103
1104 core_l4_ick: core_l4_ick {
1105 #clock-cells = <0>;
1106 compatible = "fixed-factor-clock";
1107 clocks = <&l4_ick>;
1108 clock-mult = <1>;
1109 clock-div = <1>;
1110 };
1111
1112 /* CM_FCLKEN_DSS */
1113 clock@e00 {
1114 compatible = "ti,clksel";
1115 reg = <0xe00>;
1116 #clock-cells = <2>;
1117 #address-cells = <0>;
1118
1119 dss_tv_fck: clock-dss-tv-fck {
1120 #clock-cells = <0>;
1121 compatible = "ti,gate-clock";
1122 clock-output-names = "dss_tv_fck";
1123 clocks = <&omap_54m_fck>;
1124 ti,bit-shift = <2>;
1125 };
1126
1127 dss_96m_fck: clock-dss-96m-fck {
1128 #clock-cells = <0>;
1129 compatible = "ti,gate-clock";
1130 clock-output-names = "dss_96m_fck";
1131 clocks = <&omap_96m_fck>;
1132 ti,bit-shift = <2>;
1133 };
1134
1135 dss2_alwon_fck: clock-dss2-alwon-fck {
1136 #clock-cells = <0>;
1137 compatible = "ti,gate-clock";
1138 clock-output-names = "dss2_alwon_fck";
1139 clocks = <&sys_ck>;
1140 ti,bit-shift = <1>;
1141 };
1142 };
1143
1144 dummy_ck: dummy_ck {
1145 #clock-cells = <0>;
1146 compatible = "fixed-clock";
1147 clock-frequency = <0>;
1148 };
1149
1150 /* CM_FCLKEN_WKUP */
1151 clock@c00 {
1152 compatible = "ti,clksel";
1153 reg = <0xc00>;
1154 #clock-cells = <2>;
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157
1158 gpt1_gate_fck: clock-gpt1-gate-fck@0 {
1159 reg = <0>;
1160 #clock-cells = <0>;
1161 compatible = "ti,composite-gate-clock";
1162 clock-output-names = "gpt1_gate_fck";
1163 clocks = <&sys_ck>;
1164 };
1165
1166 gpio1_dbck: clock-gpio1-dbck@3 {
1167 reg = <3>;
1168 #clock-cells = <0>;
1169 compatible = "ti,gate-clock";
1170 clock-output-names = "gpio1_dbck";
1171 clocks = <&wkup_32k_fck>;
1172 };
1173
1174 wdt2_fck: clock-wdt2-fck@5 {
1175 reg = <5>;
1176 #clock-cells = <0>;
1177 compatible = "ti,wait-gate-clock";
1178 clock-output-names = "wdt2_fck";
1179 clocks = <&wkup_32k_fck>;
1180 };
1181 };
1182
1183 gpt1_fck: gpt1_fck {
1184 #clock-cells = <0>;
1185 compatible = "ti,composite-clock";
1186 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
1187 };
1188
1189 wkup_32k_fck: wkup_32k_fck {
1190 #clock-cells = <0>;
1191 compatible = "fixed-factor-clock";
1192 clocks = <&omap_32k_fck>;
1193 clock-mult = <1>;
1194 clock-div = <1>;
1195 };
1196
1197 /* CM_ICLKEN_WKUP */
1198 clock@c10 {
1199 compatible = "ti,clksel";
1200 reg = <0xc10>;
1201 #clock-cells = <2>;
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1204
1205 wdt2_ick: clock-wdt2-ick@5 {
1206 reg = <5>;
1207 #clock-cells = <0>;
1208 compatible = "ti,omap3-interface-clock";
1209 clock-output-names = "wdt2_ick";
1210 clocks = <&wkup_l4_ick>;
1211 };
1212
1213 wdt1_ick: clock-wdt1-ick@4 {
1214 reg = <4>;
1215 #clock-cells = <0>;
1216 compatible = "ti,omap3-interface-clock";
1217 clock-output-names = "wdt1_ick";
1218 clocks = <&wkup_l4_ick>;
1219 };
1220
1221 gpio1_ick: clock-gpio1-ick@3 {
1222 reg = <3>;
1223 #clock-cells = <0>;
1224 compatible = "ti,omap3-interface-clock";
1225 clock-output-names = "gpio1_ick";
1226 clocks = <&wkup_l4_ick>;
1227 };
1228
1229 omap_32ksync_ick: clock-omap-32ksync-ick@2 {
1230 reg = <2>;
1231 #clock-cells = <0>;
1232 compatible = "ti,omap3-interface-clock";
1233 clock-output-names = "omap_32ksync_ick";
1234 clocks = <&wkup_l4_ick>;
1235 };
1236
1237 gpt12_ick: clock-gpt12-ick@1 {
1238 reg = <1>;
1239 #clock-cells = <0>;
1240 compatible = "ti,omap3-interface-clock";
1241 clock-output-names = "gpt12_ick";
1242 clocks = <&wkup_l4_ick>;
1243 };
1244
1245 gpt1_ick: clock-gpt1-ick@0 {
1246 reg = <0>;
1247 #clock-cells = <0>;
1248 compatible = "ti,omap3-interface-clock";
1249 clock-output-names = "gpt1_ick";
1250 clocks = <&wkup_l4_ick>;
1251 };
1252 };
1253
1254 per_96m_fck: per_96m_fck {
1255 #clock-cells = <0>;
1256 compatible = "fixed-factor-clock";
1257 clocks = <&omap_96m_alwon_fck>;
1258 clock-mult = <1>;
1259 clock-div = <1>;
1260 };
1261
1262 per_48m_fck: per_48m_fck {
1263 #clock-cells = <0>;
1264 compatible = "fixed-factor-clock";
1265 clocks = <&omap_48m_fck>;
1266 clock-mult = <1>;
1267 clock-div = <1>;
1268 };
1269
1270 /* CM_FCLKEN_PER */
1271 clock@1000 {
1272 compatible = "ti,clksel";
1273 reg = <0x1000>;
1274 #clock-cells = <2>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1277
1278 uart3_fck: clock-uart3-fck@11 {
1279 reg = <11>;
1280 #clock-cells = <0>;
1281 compatible = "ti,wait-gate-clock";
1282 clock-output-names = "uart3_fck";
1283 clocks = <&per_48m_fck>;
1284 };
1285
1286 gpt2_gate_fck: clock-gpt2-gate-fck@3 {
1287 reg = <3>;
1288 #clock-cells = <0>;
1289 compatible = "ti,composite-gate-clock";
1290 clock-output-names = "gpt2_gate_fck";
1291 clocks = <&sys_ck>;
1292 };
1293
1294 gpt3_gate_fck: clock-gpt3-gate-fck@4 {
1295 reg = <4>;
1296 #clock-cells = <0>;
1297 compatible = "ti,composite-gate-clock";
1298 clock-output-names = "gpt3_gate_fck";
1299 clocks = <&sys_ck>;
1300 };
1301
1302 gpt4_gate_fck: clock-gpt4-gate-fck@5 {
1303 reg = <5>;
1304 #clock-cells = <0>;
1305 compatible = "ti,composite-gate-clock";
1306 clock-output-names = "gpt4_gate_fck";
1307 clocks = <&sys_ck>;
1308 };
1309
1310 gpt5_gate_fck: clock-gpt5-gate-fck@6 {
1311 reg = <6>;
1312 #clock-cells = <0>;
1313 compatible = "ti,composite-gate-clock";
1314 clock-output-names = "gpt5_gate_fck";
1315 clocks = <&sys_ck>;
1316 };
1317
1318 gpt6_gate_fck: clock-gpt6-gate-fck@7 {
1319 reg = <7>;
1320 #clock-cells = <0>;
1321 compatible = "ti,composite-gate-clock";
1322 clock-output-names = "gpt6_gate_fck";
1323 clocks = <&sys_ck>;
1324 };
1325
1326 gpt7_gate_fck: clock-gpt7-gate-fck@8 {
1327 reg = <8>;
1328 #clock-cells = <0>;
1329 compatible = "ti,composite-gate-clock";
1330 clock-output-names = "gpt7_gate_fck";
1331 clocks = <&sys_ck>;
1332 };
1333
1334 gpt8_gate_fck: clock-gpt8-gate-fck@9 {
1335 reg = <9>;
1336 #clock-cells = <0>;
1337 compatible = "ti,composite-gate-clock";
1338 clock-output-names = "gpt8_gate_fck";
1339 clocks = <&sys_ck>;
1340 };
1341
1342 gpt9_gate_fck: clock-gpt9-gate-fck@10 {
1343 reg = <10>;
1344 #clock-cells = <0>;
1345 compatible = "ti,composite-gate-clock";
1346 clock-output-names = "gpt9_gate_fck";
1347 clocks = <&sys_ck>;
1348 };
1349
1350 gpio6_dbck: clock-gpio6-dbck@17 {
1351 reg = <17>;
1352 #clock-cells = <0>;
1353 compatible = "ti,gate-clock";
1354 clock-output-names = "gpio6_dbck";
1355 clocks = <&per_32k_alwon_fck>;
1356 };
1357
1358 gpio5_dbck: clock-gpio5-dbck@16 {
1359 reg = <16>;
1360 #clock-cells = <0>;
1361 compatible = "ti,gate-clock";
1362 clock-output-names = "gpio5_dbck";
1363 clocks = <&per_32k_alwon_fck>;
1364 };
1365
1366 gpio4_dbck: clock-gpio4-dbck@15 {
1367 reg = <15>;
1368 #clock-cells = <0>;
1369 compatible = "ti,gate-clock";
1370 clock-output-names = "gpio4_dbck";
1371 clocks = <&per_32k_alwon_fck>;
1372 };
1373
1374 gpio3_dbck: clock-gpio3-dbck@14 {
1375 reg = <14>;
1376 #clock-cells = <0>;
1377 compatible = "ti,gate-clock";
1378 clock-output-names = "gpio3_dbck";
1379 clocks = <&per_32k_alwon_fck>;
1380 };
1381
1382 gpio2_dbck: clock-gpio2-dbck@13 {
1383 reg = <13>;
1384 #clock-cells = <0>;
1385 compatible = "ti,gate-clock";
1386 clock-output-names = "gpio2_dbck";
1387 clocks = <&per_32k_alwon_fck>;
1388 };
1389
1390 wdt3_fck: clock-wdt3-fck@12 {
1391 reg = <12>;
1392 #clock-cells = <0>;
1393 compatible = "ti,wait-gate-clock";
1394 clock-output-names = "wdt3_fck";
1395 clocks = <&per_32k_alwon_fck>;
1396 };
1397
1398 mcbsp2_gate_fck: clock-mcbsp2-gate-fck@0 {
1399 reg = <0>;
1400 #clock-cells = <0>;
1401 compatible = "ti,composite-gate-clock";
1402 clock-output-names = "mcbsp2_gate_fck";
1403 clocks = <&mcbsp_clks>;
1404 };
1405
1406 mcbsp3_gate_fck: clock-mcbsp3-gate-fck@1 {
1407 reg = <1>;
1408 #clock-cells = <0>;
1409 compatible = "ti,composite-gate-clock";
1410 clock-output-names = "mcbsp3_gate_fck";
1411 clocks = <&mcbsp_clks>;
1412 };
1413
1414 mcbsp4_gate_fck: clock-mcbsp4-gate-fck@2 {
1415 reg = <2>;
1416 #clock-cells = <0>;
1417 compatible = "ti,composite-gate-clock";
1418 clock-output-names = "mcbsp4_gate_fck";
1419 clocks = <&mcbsp_clks>;
1420 };
1421 };
1422
1423 /* CM_CLKSEL_PER */
1424 clock@1040 {
1425 compatible = "ti,clksel";
1426 reg = <0x1040>;
1427 #clock-cells = <2>;
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1430
1431 gpt2_mux_fck: clock-gpt2-mux-fck@0 {
1432 reg = <0>;
1433 #clock-cells = <0>;
1434 compatible = "ti,composite-mux-clock";
1435 clock-output-names = "gpt2_mux_fck";
1436 clocks = <&omap_32k_fck>, <&sys_ck>;
1437 };
1438
1439 gpt3_mux_fck: clock-gpt3-mux-fck@1 {
1440 reg = <1>;
1441 #clock-cells = <0>;
1442 compatible = "ti,composite-mux-clock";
1443 clock-output-names = "gpt3_mux_fck";
1444 clocks = <&omap_32k_fck>, <&sys_ck>;
1445 };
1446
1447 gpt4_mux_fck: clock-gpt4-mux-fck@2 {
1448 reg = <2>;
1449 #clock-cells = <0>;
1450 compatible = "ti,composite-mux-clock";
1451 clock-output-names = "gpt4_mux_fck";
1452 clocks = <&omap_32k_fck>, <&sys_ck>;
1453 };
1454
1455 gpt5_mux_fck: clock-gpt5-mux-fck@3 {
1456 reg = <3>;
1457 #clock-cells = <0>;
1458 compatible = "ti,composite-mux-clock";
1459 clock-output-names = "gpt5_mux_fck";
1460 clocks = <&omap_32k_fck>, <&sys_ck>;
1461 };
1462
1463 gpt6_mux_fck: clock-gpt6-mux-fck@4 {
1464 reg = <4>;
1465 #clock-cells = <0>;
1466 compatible = "ti,composite-mux-clock";
1467 clock-output-names = "gpt6_mux_fck";
1468 clocks = <&omap_32k_fck>, <&sys_ck>;
1469 };
1470
1471 gpt7_mux_fck: clock-gpt7-mux-fck@5 {
1472 reg = <5>;
1473 #clock-cells = <0>;
1474 compatible = "ti,composite-mux-clock";
1475 clock-output-names = "gpt7_mux_fck";
1476 clocks = <&omap_32k_fck>, <&sys_ck>;
1477 };
1478
1479 gpt8_mux_fck: clock-gpt8-mux-fck@6 {
1480 reg = <6>;
1481 #clock-cells = <0>;
1482 compatible = "ti,composite-mux-clock";
1483 clock-output-names = "gpt8_mux_fck";
1484 clocks = <&omap_32k_fck>, <&sys_ck>;
1485 };
1486
1487 gpt9_mux_fck: clock-gpt9-mux-fck@7 {
1488 reg = <7>;
1489 #clock-cells = <0>;
1490 compatible = "ti,composite-mux-clock";
1491 clock-output-names = "gpt9_mux_fck";
1492 clocks = <&omap_32k_fck>, <&sys_ck>;
1493 };
1494 };
1495
1496 gpt2_fck: gpt2_fck {
1497 #clock-cells = <0>;
1498 compatible = "ti,composite-clock";
1499 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1500 };
1501
1502 gpt3_fck: gpt3_fck {
1503 #clock-cells = <0>;
1504 compatible = "ti,composite-clock";
1505 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1506 };
1507
1508 gpt4_fck: gpt4_fck {
1509 #clock-cells = <0>;
1510 compatible = "ti,composite-clock";
1511 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1512 };
1513
1514 gpt5_fck: gpt5_fck {
1515 #clock-cells = <0>;
1516 compatible = "ti,composite-clock";
1517 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1518 };
1519
1520 gpt6_fck: gpt6_fck {
1521 #clock-cells = <0>;
1522 compatible = "ti,composite-clock";
1523 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1524 };
1525
1526 gpt7_fck: gpt7_fck {
1527 #clock-cells = <0>;
1528 compatible = "ti,composite-clock";
1529 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1530 };
1531
1532 gpt8_fck: gpt8_fck {
1533 #clock-cells = <0>;
1534 compatible = "ti,composite-clock";
1535 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1536 };
1537
1538 gpt9_fck: gpt9_fck {
1539 #clock-cells = <0>;
1540 compatible = "ti,composite-clock";
1541 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1542 };
1543
1544 per_32k_alwon_fck: per_32k_alwon_fck {
1545 #clock-cells = <0>;
1546 compatible = "fixed-factor-clock";
1547 clocks = <&omap_32k_fck>;
1548 clock-mult = <1>;
1549 clock-div = <1>;
1550 };
1551
1552 per_l4_ick: per_l4_ick {
1553 #clock-cells = <0>;
1554 compatible = "fixed-factor-clock";
1555 clocks = <&l4_ick>;
1556 clock-mult = <1>;
1557 clock-div = <1>;
1558 };
1559
1560 /* CM_ICLKEN_PER */
1561 clock@1010 {
1562 compatible = "ti,clksel";
1563 reg = <0x1010>;
1564 #clock-cells = <2>;
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567
1568 gpio6_ick: clock-gpio6-ick@17 {
1569 reg = <17>;
1570 #clock-cells = <0>;
1571 compatible = "ti,omap3-interface-clock";
1572 clock-output-names = "gpio6_ick";
1573 clocks = <&per_l4_ick>;
1574 };
1575
1576 gpio5_ick: clock-gpio5-ick@16 {
1577 reg = <16>;
1578 #clock-cells = <0>;
1579 compatible = "ti,omap3-interface-clock";
1580 clock-output-names = "gpio5_ick";
1581 clocks = <&per_l4_ick>;
1582 };
1583
1584 gpio4_ick: clock-gpio4-ick@15 {
1585 reg = <15>;
1586 #clock-cells = <0>;
1587 compatible = "ti,omap3-interface-clock";
1588 clock-output-names = "gpio4_ick";
1589 clocks = <&per_l4_ick>;
1590 };
1591
1592 gpio3_ick: clock-gpio3-ick@14 {
1593 reg = <14>;
1594 #clock-cells = <0>;
1595 compatible = "ti,omap3-interface-clock";
1596 clock-output-names = "gpio3_ick";
1597 clocks = <&per_l4_ick>;
1598 };
1599
1600 gpio2_ick: clock-gpio2-ick@13 {
1601 reg = <13>;
1602 #clock-cells = <0>;
1603 compatible = "ti,omap3-interface-clock";
1604 clock-output-names = "gpio2_ick";
1605 clocks = <&per_l4_ick>;
1606 };
1607
1608 wdt3_ick: clock-wdt3-ick@12 {
1609 reg = <12>;
1610 #clock-cells = <0>;
1611 compatible = "ti,omap3-interface-clock";
1612 clock-output-names = "wdt3_ick";
1613 clocks = <&per_l4_ick>;
1614 };
1615
1616 uart3_ick: clock-uart3-ick@11 {
1617 reg = <11>;
1618 #clock-cells = <0>;
1619 compatible = "ti,omap3-interface-clock";
1620 clock-output-names = "uart3_ick";
1621 clocks = <&per_l4_ick>;
1622 };
1623
1624 uart4_ick: clock-uart4-ick@18 {
1625 reg = <18>;
1626 #clock-cells = <0>;
1627 compatible = "ti,omap3-interface-clock";
1628 clock-output-names = "uart4_ick";
1629 clocks = <&per_l4_ick>;
1630 };
1631
1632 gpt9_ick: clock-gpt9-ick@10 {
1633 reg = <10>;
1634 #clock-cells = <0>;
1635 compatible = "ti,omap3-interface-clock";
1636 clock-output-names = "gpt9_ick";
1637 clocks = <&per_l4_ick>;
1638 };
1639
1640 gpt8_ick: clock-gpt8-ick@9 {
1641 reg = <9>;
1642 #clock-cells = <0>;
1643 compatible = "ti,omap3-interface-clock";
1644 clock-output-names = "gpt8_ick";
1645 clocks = <&per_l4_ick>;
1646 };
1647
1648 gpt7_ick: clock-gpt7-ick@8 {
1649 reg = <8>;
1650 #clock-cells = <0>;
1651 compatible = "ti,omap3-interface-clock";
1652 clock-output-names = "gpt7_ick";
1653 clocks = <&per_l4_ick>;
1654 };
1655
1656 gpt6_ick: clock-gpt6-ick@7 {
1657 reg = <7>;
1658 #clock-cells = <0>;
1659 compatible = "ti,omap3-interface-clock";
1660 clock-output-names = "gpt6_ick";
1661 clocks = <&per_l4_ick>;
1662 };
1663
1664 gpt5_ick: clock-gpt5-ick@6 {
1665 reg = <6>;
1666 #clock-cells = <0>;
1667 compatible = "ti,omap3-interface-clock";
1668 clock-output-names = "gpt5_ick";
1669 clocks = <&per_l4_ick>;
1670 };
1671
1672 gpt4_ick: clock-gpt4-ick@5 {
1673 reg = <5>;
1674 #clock-cells = <0>;
1675 compatible = "ti,omap3-interface-clock";
1676 clock-output-names = "gpt4_ick";
1677 clocks = <&per_l4_ick>;
1678 };
1679
1680 gpt3_ick: clock-gpt3-ick@4 {
1681 reg = <4>;
1682 #clock-cells = <0>;
1683 compatible = "ti,omap3-interface-clock";
1684 clock-output-names = "gpt3_ick";
1685 clocks = <&per_l4_ick>;
1686 };
1687
1688 gpt2_ick: clock-gpt2-ick@3 {
1689 reg = <3>;
1690 #clock-cells = <0>;
1691 compatible = "ti,omap3-interface-clock";
1692 clock-output-names = "gpt2_ick";
1693 clocks = <&per_l4_ick>;
1694 };
1695
1696 mcbsp2_ick: clock-mcbsp2-ick@0 {
1697 reg = <0>;
1698 #clock-cells = <0>;
1699 compatible = "ti,omap3-interface-clock";
1700 clock-output-names = "mcbsp2_ick";
1701 clocks = <&per_l4_ick>;
1702 };
1703
1704 mcbsp3_ick: clock-mcbsp3-ick@1 {
1705 reg = <1>;
1706 #clock-cells = <0>;
1707 compatible = "ti,omap3-interface-clock";
1708 clock-output-names = "mcbsp3_ick";
1709 clocks = <&per_l4_ick>;
1710 };
1711
1712 mcbsp4_ick: clock-mcbsp4-ick@2 {
1713 reg = <2>;
1714 #clock-cells = <0>;
1715 compatible = "ti,omap3-interface-clock";
1716 clock-output-names = "mcbsp4_ick";
1717 clocks = <&per_l4_ick>;
1718 };
1719 };
1720
1721 emu_src_ck: emu_src_ck {
1722 #clock-cells = <0>;
1723 compatible = "ti,clkdm-gate-clock";
1724 clocks = <&emu_src_mux_ck>;
1725 };
1726
1727 secure_32k_fck: secure_32k_fck {
1728 #clock-cells = <0>;
1729 compatible = "fixed-clock";
1730 clock-frequency = <32768>;
1731 };
1732
1733 gpt12_fck: gpt12_fck {
1734 #clock-cells = <0>;
1735 compatible = "fixed-factor-clock";
1736 clocks = <&secure_32k_fck>;
1737 clock-mult = <1>;
1738 clock-div = <1>;
1739 };
1740
1741 wdt1_fck: wdt1_fck {
1742 #clock-cells = <0>;
1743 compatible = "fixed-factor-clock";
1744 clocks = <&secure_32k_fck>;
1745 clock-mult = <1>;
1746 clock-div = <1>;
1747 };
1748 };
1749
1750 &cm_clockdomains {
1751 core_l3_clkdm: core_l3_clkdm {
1752 compatible = "ti,clockdomain";
1753 clocks = <&sdrc_ick>;
1754 };
1755
1756 dpll3_clkdm: dpll3_clkdm {
1757 compatible = "ti,clockdomain";
1758 clocks = <&dpll3_ck>;
1759 };
1760
1761 dpll1_clkdm: dpll1_clkdm {
1762 compatible = "ti,clockdomain";
1763 clocks = <&dpll1_ck>;
1764 };
1765
1766 per_clkdm: per_clkdm {
1767 compatible = "ti,clockdomain";
1768 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1769 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1770 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1771 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1772 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1773 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1774 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1775 <&mcbsp4_ick>;
1776 };
1777
1778 emu_clkdm: emu_clkdm {
1779 compatible = "ti,clockdomain";
1780 clocks = <&emu_src_ck>;
1781 };
1782
1783 dpll4_clkdm: dpll4_clkdm {
1784 compatible = "ti,clockdomain";
1785 clocks = <&dpll4_ck>;
1786 };
1787
1788 wkup_clkdm: wkup_clkdm {
1789 compatible = "ti,clockdomain";
1790 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1791 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1792 <&gpt1_ick>;
1793 };
1794
1795 dss_clkdm: dss_clkdm {
1796 compatible = "ti,clockdomain";
1797 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1798 };
1799
1800 core_l4_clkdm: core_l4_clkdm {
1801 compatible = "ti,clockdomain";
1802 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1803 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1804 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1805 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1806 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1807 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1808 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1809 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1810 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1811 };
1812 };
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