1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
12
13 / {
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 chosen { };
19
20 aliases {
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 i2c3 = &i2c4;
25 mmc0 = &mmc1;
26 mmc1 = &mmc2;
27 mmc2 = &mmc3;
28 mmc3 = &mmc4;
29 mmc4 = &mmc5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 rproc0 = &dsp;
35 rproc1 = &ipu;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 compatible = "arm,cortex-a9";
44 device_type = "cpu";
45 next-level-cache = <&L2>;
46 reg = <0x0>;
47
48 clocks = <&dpll_mpu_ck>;
49 clock-names = "cpu";
50
51 clock-latency = <300000>; /* From omap-cpufreq driver */
52 };
53 cpu@1 {
54 compatible = "arm,cortex-a9";
55 device_type = "cpu";
56 next-level-cache = <&L2>;
57 reg = <0x1>;
58 };
59 };
60
61 /*
62 * Needed early by omap4_sram_init() for barrier, do not move to l3
63 * interconnect as simple-pm-bus probes at module_init() time.
64 */
65 ocmcram: sram@40304000 {
66 compatible = "mmio-sram";
67 reg = <0x40304000 0xa000>; /* 40k */
68 };
69
70 gic: interrupt-controller@48241000 {
71 compatible = "arm,cortex-a9-gic";
72 interrupt-controller;
73 #interrupt-cells = <3>;
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
76 interrupt-parent = <&gic>;
77 };
78
79 L2: cache-controller@48242000 {
80 compatible = "arm,pl310-cache";
81 reg = <0x48242000 0x1000>;
82 cache-unified;
83 cache-level = <2>;
84 };
85
86 local-timer@48240600 {
87 compatible = "arm,cortex-a9-twd-timer";
88 clocks = <&mpu_periphclk>;
89 reg = <0x48240600 0x20>;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
91 interrupt-parent = <&gic>;
92 };
93
94 wakeupgen: interrupt-controller@48281000 {
95 compatible = "ti,omap4-wugen-mpu";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = <0x48281000 0x1000>;
99 interrupt-parent = <&gic>;
100 };
101
102 /*
103 * XXX: Use a flat representation of the OMAP4 interconnect.
104 * The real OMAP interconnect network is quite complex.
105 * Since it will not bring real advantage to represent that in DT for
106 * the moment, just use a fake OCP bus entry to represent the whole bus
107 * hierarchy.
108 */
109 ocp {
110 compatible = "simple-pm-bus";
111 power-domains = <&prm_l4per>;
112 clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
113 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
114 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118
119 l3-noc@44000000 {
120 compatible = "ti,omap4-l3-noc";
121 reg = <0x44000000 0x1000>,
122 <0x44800000 0x2000>,
123 <0x45000000 0x1000>;
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 l4_wkup: interconnect@4a300000 {
129 };
130
131 l4_cfg: interconnect@4a000000 {
132 };
133
134 l4_per: interconnect@48000000 {
135 };
136
137 target-module@48210000 {
138 compatible = "ti,sysc-omap4-simple", "ti,sysc";
139 power-domains = <&prm_mpu>;
140 clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
141 clock-names = "fck";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0 0x48210000 0x1f0000>;
145
146 mpu {
147 compatible = "ti,omap4-mpu";
148 sram = <&ocmcram>;
149 };
150 };
151
152 l4_abe: interconnect@40100000 {
153 };
154
155 target-module@50000000 {
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 reg = <0x50000000 4>,
158 <0x50000010 4>,
159 <0x50000014 4>;
160 reg-names = "rev", "sysc", "syss";
161 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
162 <SYSC_IDLE_NO>,
163 <SYSC_IDLE_SMART>;
164 ti,syss-mask = <1>;
165 ti,no-idle-on-init;
166 clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
167 clock-names = "fck";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
171 <0x00000000 0x00000000 0x40000000>; /* data */
172
173 gpmc: gpmc@50000000 {
174 compatible = "ti,omap4430-gpmc";
175 reg = <0x50000000 0x1000>;
176 #address-cells = <2>;
177 #size-cells = <1>;
178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&sdma 4>;
180 dma-names = "rxtx";
181 gpmc,num-cs = <8>;
182 gpmc,num-waitpins = <4>;
183 clocks = <&l3_div_ck>;
184 clock-names = "fck";
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 };
190 };
191
192 target-module@52000000 {
193 compatible = "ti,sysc-omap4", "ti,sysc";
194 reg = <0x52000000 0x4>,
195 <0x52000010 0x4>;
196 reg-names = "rev", "sysc";
197 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_NO>,
200 <SYSC_IDLE_SMART>,
201 <SYSC_IDLE_SMART_WKUP>;
202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 <SYSC_IDLE_NO>,
204 <SYSC_IDLE_SMART>,
205 <SYSC_IDLE_SMART_WKUP>;
206 ti,sysc-delay-us = <2>;
207 power-domains = <&prm_cam>;
208 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
209 clock-names = "fck";
210 #address-cells = <1>;
211 #size-cells = <1>;
212 ranges = <0 0x52000000 0x1000000>;
213
214 /* No child device binding, driver in staging */
215 };
216
217 /*
218 * Note that 4430 needs cross trigger interface (CTI) supported
219 * before we can configure the interrupts. This means sampling
220 * events are not supported for pmu. Note that 4460 does not use
221 * CTI, see also 4460.dtsi.
222 */
223 target-module@54000000 {
224 compatible = "ti,sysc-omap4-simple", "ti,sysc";
225 power-domains = <&prm_emu>;
226 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
227 clock-names = "fck";
228 #address-cells = <1>;
229 #size-cells = <1>;
230 ranges = <0x0 0x54000000 0x1000000>;
231
232 pmu: pmu {
233 compatible = "arm,cortex-a9-pmu";
234 };
235 };
236
237 target-module@55082000 {
238 compatible = "ti,sysc-omap2", "ti,sysc";
239 reg = <0x55082000 0x4>,
240 <0x55082010 0x4>,
241 <0x55082014 0x4>;
242 reg-names = "rev", "sysc", "syss";
243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
244 <SYSC_IDLE_NO>,
245 <SYSC_IDLE_SMART>;
246 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
247 SYSC_OMAP2_SOFTRESET |
248 SYSC_OMAP2_AUTOIDLE)>;
249 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
250 clock-names = "fck";
251 resets = <&prm_core 2>;
252 reset-names = "rstctrl";
253 ranges = <0x0 0x55082000 0x100>;
254 #size-cells = <1>;
255 #address-cells = <1>;
256
257 mmu_ipu: mmu@0 {
258 compatible = "ti,omap4-iommu";
259 reg = <0x0 0x100>;
260 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
261 #iommu-cells = <0>;
262 ti,iommu-bus-err-back;
263 };
264 };
265
266 target-module@4012c000 {
267 compatible = "ti,sysc-omap4", "ti,sysc";
268 reg = <0x4012c000 0x4>,
269 <0x4012c010 0x4>;
270 reg-names = "rev", "sysc";
271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
273 <SYSC_IDLE_NO>,
274 <SYSC_IDLE_SMART>,
275 <SYSC_IDLE_SMART_WKUP>;
276 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
277 clock-names = "fck";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
281 <0x4902c000 0x4902c000 0x1000>; /* L3 */
282
283 /* No child device binding or driver in mainline */
284 };
285
286 target-module@4e000000 {
287 compatible = "ti,sysc-omap2", "ti,sysc";
288 reg = <0x4e000000 0x4>,
289 <0x4e000010 0x4>;
290 reg-names = "rev", "sysc";
291 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
292 <SYSC_IDLE_NO>,
293 <SYSC_IDLE_SMART>;
294 ranges = <0x0 0x4e000000 0x2000000>;
295 #size-cells = <1>;
296 #address-cells = <1>;
297
298 dmm@0 {
299 compatible = "ti,omap4-dmm";
300 reg = <0 0x800>;
301 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
302 };
303 };
304
305 target-module@4c000000 {
306 compatible = "ti,sysc-omap4-simple", "ti,sysc";
307 reg = <0x4c000000 0x4>;
308 reg-names = "rev";
309 clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
310 clock-names = "fck";
311 ti,no-idle;
312 #address-cells = <1>;
313 #size-cells = <1>;
314 ranges = <0x0 0x4c000000 0x1000000>;
315
316 emif1: emif@0 {
317 compatible = "ti,emif-4d";
318 reg = <0 0x100>;
319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
320 phy-type = <1>;
321 hw-caps-read-idle-ctrl;
322 hw-caps-ll-interface;
323 hw-caps-temp-alert;
324 };
325 };
326
327 target-module@4d000000 {
328 compatible = "ti,sysc-omap4-simple", "ti,sysc";
329 reg = <0x4d000000 0x4>;
330 reg-names = "rev";
331 clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
332 clock-names = "fck";
333 ti,no-idle;
334 #address-cells = <1>;
335 #size-cells = <1>;
336 ranges = <0x0 0x4d000000 0x1000000>;
337
338 emif2: emif@0 {
339 compatible = "ti,emif-4d";
340 reg = <0 0x100>;
341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
342 phy-type = <1>;
343 hw-caps-read-idle-ctrl;
344 hw-caps-ll-interface;
345 hw-caps-temp-alert;
346 };
347 };
348
349 dsp: dsp {
350 compatible = "ti,omap4-dsp";
351 ti,bootreg = <&scm_conf 0x304 0>;
352 iommus = <&mmu_dsp>;
353 resets = <&prm_tesla 0>;
354 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
355 firmware-name = "omap4-dsp-fw.xe64T";
356 mboxes = <&mailbox &mbox_dsp>;
357 status = "disabled";
358 };
359
360 ipu: ipu@55020000 {
361 compatible = "ti,omap4-ipu";
362 reg = <0x55020000 0x10000>;
363 reg-names = "l2ram";
364 iommus = <&mmu_ipu>;
365 resets = <&prm_core 0>, <&prm_core 1>;
366 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
367 firmware-name = "omap4-ipu-fw.xem3";
368 mboxes = <&mailbox &mbox_ipu>;
369 status = "disabled";
370 };
371
372 aes1_target: target-module@4b501000 {
373 compatible = "ti,sysc-omap2", "ti,sysc";
374 reg = <0x4b501080 0x4>,
375 <0x4b501084 0x4>,
376 <0x4b501088 0x4>;
377 reg-names = "rev", "sysc", "syss";
378 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
379 SYSC_OMAP2_AUTOIDLE)>;
380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
381 <SYSC_IDLE_NO>,
382 <SYSC_IDLE_SMART>,
383 <SYSC_IDLE_SMART_WKUP>;
384 ti,syss-mask = <1>;
385 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
386 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
387 clock-names = "fck";
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges = <0x0 0x4b501000 0x1000>;
391
392 aes1: aes@0 {
393 compatible = "ti,omap4-aes";
394 reg = <0 0xa0>;
395 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
396 dmas = <&sdma 111>, <&sdma 110>;
397 dma-names = "tx", "rx";
398 };
399 };
400
401 aes2_target: target-module@4b701000 {
402 compatible = "ti,sysc-omap2", "ti,sysc";
403 reg = <0x4b701080 0x4>,
404 <0x4b701084 0x4>,
405 <0x4b701088 0x4>;
406 reg-names = "rev", "sysc", "syss";
407 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
408 SYSC_OMAP2_AUTOIDLE)>;
409 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
410 <SYSC_IDLE_NO>,
411 <SYSC_IDLE_SMART>,
412 <SYSC_IDLE_SMART_WKUP>;
413 ti,syss-mask = <1>;
414 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
415 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
416 clock-names = "fck";
417 #address-cells = <1>;
418 #size-cells = <1>;
419 ranges = <0x0 0x4b701000 0x1000>;
420
421 aes2: aes@0 {
422 compatible = "ti,omap4-aes";
423 reg = <0 0xa0>;
424 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
425 dmas = <&sdma 114>, <&sdma 113>;
426 dma-names = "tx", "rx";
427 };
428 };
429
430 sham_target: target-module@4b100000 {
431 compatible = "ti,sysc-omap3-sham", "ti,sysc";
432 reg = <0x4b100100 0x4>,
433 <0x4b100110 0x4>,
434 <0x4b100114 0x4>;
435 reg-names = "rev", "sysc", "syss";
436 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
437 SYSC_OMAP2_AUTOIDLE)>;
438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
439 <SYSC_IDLE_NO>,
440 <SYSC_IDLE_SMART>;
441 ti,syss-mask = <1>;
442 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
443 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
444 clock-names = "fck";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 ranges = <0x0 0x4b100000 0x1000>;
448
449 sham: sham@0 {
450 compatible = "ti,omap4-sham";
451 reg = <0 0x300>;
452 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
453 dmas = <&sdma 119>;
454 dma-names = "rx";
455 };
456 };
457
458 abb_mpu: regulator-abb-mpu {
459 compatible = "ti,abb-v2";
460 regulator-name = "abb_mpu";
461 #address-cells = <0>;
462 #size-cells = <0>;
463 ti,tranxdone-status-mask = <0x80>;
464 clocks = <&sys_clkin_ck>;
465 ti,settling-time = <50>;
466 ti,clock-cycles = <16>;
467
468 status = "disabled";
469 };
470
471 abb_iva: regulator-abb-iva {
472 compatible = "ti,abb-v2";
473 regulator-name = "abb_iva";
474 #address-cells = <0>;
475 #size-cells = <0>;
476 ti,tranxdone-status-mask = <0x80000000>;
477 clocks = <&sys_clkin_ck>;
478 ti,settling-time = <50>;
479 ti,clock-cycles = <16>;
480
481 status = "disabled";
482 };
483
484 sgx_module: target-module@56000000 {
485 compatible = "ti,sysc-omap4", "ti,sysc";
486 reg = <0x5600fe00 0x4>,
487 <0x5600fe10 0x4>;
488 reg-names = "rev", "sysc";
489 ti,sysc-midle = <SYSC_IDLE_FORCE>,
490 <SYSC_IDLE_NO>,
491 <SYSC_IDLE_SMART>,
492 <SYSC_IDLE_SMART_WKUP>;
493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
494 <SYSC_IDLE_NO>,
495 <SYSC_IDLE_SMART>,
496 <SYSC_IDLE_SMART_WKUP>;
497 power-domains = <&prm_gfx>;
498 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
499 clock-names = "fck";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0 0x56000000 0x2000000>;
503
504 gpu@0 {
505 compatible = "ti,omap4430-gpu", "img,powervr-sgx540";
506 reg = <0x0 0x2000000>; /* 32MB */
507 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
508 };
509 };
510
511 /*
512 * DSS is only using l3 mapping without l4 as noted in the TRM
513 * "10.1.3 DSS Register Manual" for omap4460.
514 */
515 target-module@58000000 {
516 compatible = "ti,sysc-omap2", "ti,sysc";
517 reg = <0x58000000 4>,
518 <0x58000014 4>;
519 reg-names = "rev", "syss";
520 ti,syss-mask = <1>;
521 power-domains = <&prm_dss>;
522 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
523 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
524 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
525 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
526 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
527 #address-cells = <1>;
528 #size-cells = <1>;
529 ranges = <0 0x58000000 0x1000000>;
530
531 dss: dss@0 {
532 compatible = "ti,omap4-dss";
533 reg = <0 0x80>;
534 status = "disabled";
535 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
536 clock-names = "fck";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges = <0 0 0x1000000>;
540
541 target-module@1000 {
542 compatible = "ti,sysc-omap2", "ti,sysc";
543 reg = <0x1000 0x4>,
544 <0x1010 0x4>,
545 <0x1014 0x4>;
546 reg-names = "rev", "sysc", "syss";
547 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
548 <SYSC_IDLE_NO>,
549 <SYSC_IDLE_SMART>;
550 ti,sysc-midle = <SYSC_IDLE_FORCE>,
551 <SYSC_IDLE_NO>,
552 <SYSC_IDLE_SMART>;
553 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
554 SYSC_OMAP2_ENAWAKEUP |
555 SYSC_OMAP2_SOFTRESET |
556 SYSC_OMAP2_AUTOIDLE)>;
557 ti,syss-mask = <1>;
558 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
559 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
560 clock-names = "fck", "sys_clk";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0 0x1000 0x1000>;
564
565 dispc@0 {
566 compatible = "ti,omap4-dispc";
567 reg = <0 0x1000>;
568 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
570 clock-names = "fck";
571 };
572 };
573
574 target-module@2000 {
575 compatible = "ti,sysc-omap2", "ti,sysc";
576 reg = <0x2000 0x4>,
577 <0x2010 0x4>,
578 <0x2014 0x4>;
579 reg-names = "rev", "sysc", "syss";
580 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
581 <SYSC_IDLE_NO>,
582 <SYSC_IDLE_SMART>;
583 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
584 SYSC_OMAP2_AUTOIDLE)>;
585 ti,syss-mask = <1>;
586 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
587 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
588 clock-names = "fck", "sys_clk";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges = <0 0x2000 0x1000>;
592
593 rfbi: encoder@0 {
594 reg = <0 0x1000>;
595 status = "disabled";
596 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
597 clock-names = "fck", "ick";
598 };
599 };
600
601 target-module@3000 {
602 compatible = "ti,sysc-omap2", "ti,sysc";
603 reg = <0x3000 0x4>;
604 reg-names = "rev";
605 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
606 clock-names = "sys_clk";
607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges = <0 0x3000 0x1000>;
610
611 venc: encoder@0 {
612 compatible = "ti,omap4-venc";
613 reg = <0 0x1000>;
614 status = "disabled";
615 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
616 clock-names = "fck";
617 };
618 };
619
620 target-module@4000 {
621 compatible = "ti,sysc-omap2", "ti,sysc";
622 reg = <0x4000 0x4>,
623 <0x4010 0x4>,
624 <0x4014 0x4>;
625 reg-names = "rev", "sysc", "syss";
626 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
627 <SYSC_IDLE_NO>,
628 <SYSC_IDLE_SMART>;
629 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
630 SYSC_OMAP2_ENAWAKEUP |
631 SYSC_OMAP2_SOFTRESET |
632 SYSC_OMAP2_AUTOIDLE)>;
633 ti,syss-mask = <1>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges = <0 0x4000 0x1000>;
637
638 dsi1: encoder@0 {
639 compatible = "ti,omap4-dsi";
640 reg = <0 0x200>,
641 <0x200 0x40>,
642 <0x300 0x20>;
643 reg-names = "proto", "phy", "pll";
644 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
645 status = "disabled";
646 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
647 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
648 clock-names = "fck", "sys_clk";
649
650 #address-cells = <1>;
651 #size-cells = <0>;
652 };
653 };
654
655 target-module@5000 {
656 compatible = "ti,sysc-omap2", "ti,sysc";
657 reg = <0x5000 0x4>,
658 <0x5010 0x4>,
659 <0x5014 0x4>;
660 reg-names = "rev", "sysc", "syss";
661 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
662 <SYSC_IDLE_NO>,
663 <SYSC_IDLE_SMART>;
664 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
665 SYSC_OMAP2_ENAWAKEUP |
666 SYSC_OMAP2_SOFTRESET |
667 SYSC_OMAP2_AUTOIDLE)>;
668 ti,syss-mask = <1>;
669 #address-cells = <1>;
670 #size-cells = <1>;
671 ranges = <0 0x5000 0x1000>;
672
673 dsi2: encoder@0 {
674 compatible = "ti,omap4-dsi";
675 reg = <0 0x200>,
676 <0x200 0x40>,
677 <0x300 0x20>;
678 reg-names = "proto", "phy", "pll";
679 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
680 status = "disabled";
681 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
682 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
683 clock-names = "fck", "sys_clk";
684
685 #address-cells = <1>;
686 #size-cells = <0>;
687 };
688 };
689
690 target-module@6000 {
691 compatible = "ti,sysc-omap4", "ti,sysc";
692 reg = <0x6000 0x4>,
693 <0x6010 0x4>;
694 reg-names = "rev", "sysc";
695 /*
696 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
697 * but HDMI audio will fail with them.
698 */
699 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
700 <SYSC_IDLE_NO>;
701 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
702 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
703 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
704 clock-names = "fck", "dss_clk";
705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges = <0 0x6000 0x2000>;
708
709 hdmi: encoder@0 {
710 compatible = "ti,omap4-hdmi";
711 reg = <0 0x200>,
712 <0x200 0x100>,
713 <0x300 0x100>,
714 <0x400 0x1000>;
715 reg-names = "wp", "pll", "phy", "core";
716 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
717 status = "disabled";
718 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
719 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
720 clock-names = "fck", "sys_clk";
721 dmas = <&sdma 76>;
722 dma-names = "audio_tx";
723 };
724 };
725 };
726 };
727
728 iva_hd_target: target-module@5a000000 {
729 compatible = "ti,sysc-omap4", "ti,sysc";
730 reg = <0x5a05a400 0x4>,
731 <0x5a05a410 0x4>;
732 reg-names = "rev", "sysc";
733 ti,sysc-midle = <SYSC_IDLE_FORCE>,
734 <SYSC_IDLE_NO>,
735 <SYSC_IDLE_SMART>;
736 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
737 <SYSC_IDLE_NO>,
738 <SYSC_IDLE_SMART>;
739 power-domains = <&prm_ivahd>;
740 resets = <&prm_ivahd 2>;
741 reset-names = "rstctrl";
742 clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
743 clock-names = "fck";
744 #address-cells = <1>;
745 #size-cells = <1>;
746 ranges = <0x5a000000 0x5a000000 0x1000000>,
747 <0x5b000000 0x5b000000 0x1000000>;
748
749 iva {
750 compatible = "ti,ivahd";
751 };
752 };
753 };
754 };
755
756 #include "omap4-l4.dtsi"
757 #include "omap4-l4-abe.dtsi"
758 #include "omap44xx-clocks.dtsi"
759
760 &prm {
761 prm_mpu: prm@300 {
762 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
763 reg = <0x300 0x100>;
764 #power-domain-cells = <0>;
765 };
766
767 prm_tesla: prm@400 {
768 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
769 reg = <0x400 0x100>;
770 #reset-cells = <1>;
771 #power-domain-cells = <0>;
772 };
773
774 prm_abe: prm@500 {
775 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
776 reg = <0x500 0x100>;
777 #power-domain-cells = <0>;
778 };
779
780 prm_always_on_core: prm@600 {
781 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
782 reg = <0x600 0x100>;
783 #power-domain-cells = <0>;
784 };
785
786 prm_core: prm@700 {
787 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
788 reg = <0x700 0x100>;
789 #reset-cells = <1>;
790 #power-domain-cells = <0>;
791 };
792
793 prm_ivahd: prm@f00 {
794 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
795 reg = <0xf00 0x100>;
796 #reset-cells = <1>;
797 #power-domain-cells = <0>;
798 };
799
800 prm_cam: prm@1000 {
801 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
802 reg = <0x1000 0x100>;
803 #power-domain-cells = <0>;
804 };
805
806 prm_dss: prm@1100 {
807 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
808 reg = <0x1100 0x100>;
809 #power-domain-cells = <0>;
810 };
811
812 prm_gfx: prm@1200 {
813 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
814 reg = <0x1200 0x100>;
815 #power-domain-cells = <0>;
816 };
817
818 prm_l3init: prm@1300 {
819 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
820 reg = <0x1300 0x100>;
821 #power-domain-cells = <0>;
822 };
823
824 prm_l4per: prm@1400 {
825 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
826 reg = <0x1400 0x100>;
827 #power-domain-cells = <0>;
828 };
829
830 prm_cefuse: prm@1600 {
831 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
832 reg = <0x1600 0x100>;
833 #power-domain-cells = <0>;
834 };
835
836 prm_wkup: prm@1700 {
837 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
838 reg = <0x1700 0x100>;
839 #power-domain-cells = <0>;
840 };
841
842 prm_emu: prm@1900 {
843 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
844 reg = <0x1900 0x100>;
845 #power-domain-cells = <0>;
846 };
847
848 prm_dss: prm@1100 {
849 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
850 reg = <0x1100 0x40>;
851 #power-domain-cells = <0>;
852 };
853
854 prm_device: prm@1b00 {
855 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
856 reg = <0x1b00 0x40>;
857 #reset-cells = <1>;
858 };
859 };
860
861 /* Preferred always-on timer for clockevent */
862 &timer1_target {
863 ti,no-reset-on-init;
864 ti,no-idle;
865 timer@0 {
866 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
867 assigned-clock-parents = <&sys_32k_ck>;
868 };
869 };
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