1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Device Tree Source for OMAP4460 SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7 #include "omap4.dtsi"
8
9 / {
10 cpus {
11 /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
12 cpu0: cpu@0 {
13 operating-points = <
14 /* kHz uV */
15 350000 1025000
16 700000 1200000
17 920000 1313000
18 >;
19 clock-latency = <300000>; /* From legacy driver */
20
21 /* cooling options */
22 #cooling-cells = <2>; /* min followed by max */
23 };
24 };
25
26 thermal-zones {
27 #include "omap4-cpu-thermal.dtsi"
28 };
29
30 ocp {
31 bandgap: bandgap@4a002260 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
35 compatible = "ti,omap4460-bandgap";
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
37 gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
38
39 #thermal-sensor-cells = <0>;
40 };
41
42 abb_mpu: regulator-abb-mpu {
43 status = "okay";
44
45 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
46 <0x4A002268 0x4>;
47 reg-names = "base-address", "int-address",
48 "efuse-address";
49
50 ti,abb_info = <
51 /*uV ABB efuse rbb_m fbb_m vset_m*/
52 1025000 0 0 0 0 0
53 1200000 0 0 0 0 0
54 1313000 0 0 0x100000 0x40000 0
55 1375000 1 0 0 0 0
56 1389000 1 0 0 0 0
57 >;
58 };
59
60 abb_iva: regulator-abb-iva {
61 status = "okay";
62
63 reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
64 <0x4A002268 0x4>;
65 reg-names = "base-address", "int-address",
66 "efuse-address";
67
68 ti,abb_info = <
69 /*uV ABB efuse rbb_m fbb_m vset_m*/
70 950000 0 0 0 0 0
71 1140000 0 0 0 0 0
72 1291000 0 0 0x200000 0 0
73 1375000 1 0 0 0 0
74 1376000 1 0 0 0 0
75 >;
76 };
77 };
78
79 };
80
81 &cpu_thermal {
82 thermal-sensors = <&bandgap>;
83 coefficients = <348 (-9301)>;
84 };
85
86 /* Only some L4 CFG interconnect ranges are different on 4460 */
87 &l4_cfg_segment_300000 {
88 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
89 <0x00040000 0x00340000 0x001000>, /* ap 68 */
90 <0x00020000 0x00320000 0x004000>, /* ap 71 */
91 <0x00024000 0x00324000 0x002000>, /* ap 72 */
92 <0x00026000 0x00326000 0x001000>, /* ap 73 */
93 <0x00027000 0x00327000 0x001000>, /* ap 74 */
94 <0x00028000 0x00328000 0x001000>, /* ap 75 */
95 <0x00029000 0x00329000 0x001000>, /* ap 76 */
96 <0x00030000 0x00330000 0x010000>, /* ap 77 */
97 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
98 <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
99 <0x00010000 0x00310000 0x008000>, /* ap 92 */
100 <0x00018000 0x00318000 0x004000>, /* ap 93 */
101 <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
102 <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
103 };
104
105 &l4_cfg_target_0 {
106 ranges = <0x00000000 0x00000000 0x00010000>,
107 <0x00010000 0x00010000 0x00008000>,
108 <0x00018000 0x00018000 0x00004000>,
109 <0x0001c000 0x0001c000 0x00002000>,
110 <0x0001e000 0x0001e000 0x00002000>,
111 <0x00020000 0x00020000 0x00004000>,
112 <0x00024000 0x00024000 0x00002000>,
113 <0x00026000 0x00026000 0x00001000>,
114 <0x00027000 0x00027000 0x00001000>,
115 <0x00028000 0x00028000 0x00001000>,
116 <0x00029000 0x00029000 0x00001000>,
117 <0x0002a000 0x0002a000 0x00002000>,
118 <0x0002c000 0x0002c000 0x00004000>,
119 <0x00030000 0x00030000 0x00010000>;
120 };
121
122 &pmu {
123 compatible = "arm,cortex-a9-pmu";
124 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 /include/ "omap446x-clocks.dtsi"
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