1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 chosen {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinner,simple-framebuffer",
28 "simple-framebuffer";
29 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCON0>,
31 <&display_clocks CLK_MIXER0>;
32 status = "disabled";
33 };
34
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinner,simple-framebuffer",
37 "simple-framebuffer";
38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled";
42 };
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 compatible = "arm,cortex-a53";
51 device_type = "cpu";
52 reg = <0>;
53 enable-method = "psci";
54 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&l2_cache>;
64 };
65
66 cpu1: cpu@1 {
67 compatible = "arm,cortex-a53";
68 device_type = "cpu";
69 reg = <1>;
70 enable-method = "psci";
71 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu";
73 #cooling-cells = <2>;
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <256>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l2_cache>;
81 };
82
83 cpu2: cpu@2 {
84 compatible = "arm,cortex-a53";
85 device_type = "cpu";
86 reg = <2>;
87 enable-method = "psci";
88 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_cache>;
98 };
99
100 cpu3: cpu@3 {
101 compatible = "arm,cortex-a53";
102 device_type = "cpu";
103 reg = <3>;
104 enable-method = "psci";
105 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu";
107 #cooling-cells = <2>;
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&l2_cache>;
115 };
116
117 l2_cache: l2-cache {
118 compatible = "cache";
119 cache-level = <2>;
120 cache-unified;
121 cache-size = <0x80000>;
122 cache-line-size = <64>;
123 cache-sets = <512>;
124 };
125 };
126
127 de: display-engine {
128 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0>,
130 <&mixer1>;
131 status = "disabled";
132 };
133
134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points-v2";
136
137 opp-432000000 {
138 opp-hz = /bits/ 64 <432000000>;
139 };
140 };
141
142 osc24M: osc24M-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
147 };
148
149 osc32k: osc32k-clk {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc32k";
154 };
155
156 pmu {
157 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 };
164
165 psci {
166 compatible = "arm,psci-0.2";
167 method = "smc";
168 };
169
170 sound: sound {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing =
177 "Left DAC", "DACL",
178 "Right DAC", "DACR",
179 "ADCL", "Left ADC",
180 "ADCR", "Right ADC";
181 status = "disabled";
182
183 simple-audio-card,dai-link@0 {
184 format = "i2s";
185 frame-master = <&link0_cpu>;
186 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>;
188
189 link0_cpu: cpu {
190 sound-dai = <&dai>;
191 };
192
193 link0_codec: codec {
194 sound-dai = <&codec 0>;
195 };
196 };
197 };
198
199 timer {
200 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 };
212
213 thermal-zones {
214 cpu_thermal: cpu0-thermal {
215 /* milliseconds */
216 polling-delay-passive = <0>;
217 polling-delay = <0>;
218 thermal-sensors = <&ths 0>;
219
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 };
228 map1 {
229 trip = <&cpu_alert1>;
230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 };
235 };
236
237 trips {
238 cpu_alert0: cpu-alert0 {
239 /* milliCelsius */
240 temperature = <75000>;
241 hysteresis = <2000>;
242 type = "passive";
243 };
244
245 cpu_alert1: cpu-alert1 {
246 /* milliCelsius */
247 temperature = <90000>;
248 hysteresis = <2000>;
249 type = "hot";
250 };
251
252 cpu_crit: cpu-crit {
253 /* milliCelsius */
254 temperature = <110000>;
255 hysteresis = <2000>;
256 type = "critical";
257 };
258 };
259 };
260
261 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */
263 polling-delay-passive = <0>;
264 polling-delay = <0>;
265 thermal-sensors = <&ths 1>;
266
267 trips {
268 gpu0_crit: gpu0-crit {
269 temperature = <110000>;
270 hysteresis = <2000>;
271 type = "critical";
272 };
273 };
274 };
275
276 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */
278 polling-delay-passive = <0>;
279 polling-delay = <0>;
280 thermal-sensors = <&ths 2>;
281
282 trips {
283 gpu1_crit: gpu1-crit {
284 temperature = <110000>;
285 hysteresis = <2000>;
286 type = "critical";
287 };
288 };
289 };
290 };
291
292 soc {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 ranges;
297
298 bus@1000000 {
299 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>;
303 #size-cells = <1>;
304 ranges = <0 0x1000000 0x400000>;
305
306 display_clocks: clock@0 {
307 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x10000>;
309 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu CLK_DE>;
311 clock-names = "bus",
312 "mod";
313 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = <1>;
315 #reset-cells = <1>;
316 };
317
318 rotate: rotate@20000 {
319 compatible = "allwinner,sun50i-a64-de2-rotate",
320 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 0x10000>;
322 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&display_clocks CLK_ROT>;
325 clock-names = "bus",
326 "mod";
327 resets = <&display_clocks RST_ROT>;
328 };
329
330 mixer0: mixer@100000 {
331 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x100000 0x100000>;
333 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&display_clocks CLK_MIXER0>;
335 clock-names = "bus",
336 "mod";
337 resets = <&display_clocks RST_MIXER0>;
338
339 ports {
340 #address-cells = <1>;
341 #size-cells = <0>;
342
343 mixer0_out: port@1 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <1>;
347
348 mixer0_out_tcon0: endpoint@0 {
349 reg = <0>;
350 remote-endpoint = <&tcon0_in_mixer0>;
351 };
352
353 mixer0_out_tcon1: endpoint@1 {
354 reg = <1>;
355 remote-endpoint = <&tcon1_in_mixer0>;
356 };
357 };
358 };
359 };
360
361 mixer1: mixer@200000 {
362 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x200000 0x100000>;
364 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&display_clocks CLK_MIXER1>;
366 clock-names = "bus",
367 "mod";
368 resets = <&display_clocks RST_MIXER1>;
369
370 ports {
371 #address-cells = <1>;
372 #size-cells = <0>;
373
374 mixer1_out: port@1 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 reg = <1>;
378
379 mixer1_out_tcon0: endpoint@0 {
380 reg = <0>;
381 remote-endpoint = <&tcon0_in_mixer1>;
382 };
383
384 mixer1_out_tcon1: endpoint@1 {
385 reg = <1>;
386 remote-endpoint = <&tcon1_in_mixer1>;
387 };
388 };
389 };
390 };
391 };
392
393 syscon: syscon@1c00000 {
394 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ranges;
399
400 sram_c: sram@18000 {
401 compatible = "mmio-sram";
402 reg = <0x00018000 0x28000>;
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0x00018000 0x28000>;
406
407 de2_sram: sram-section@0 {
408 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = <0x0000 0x28000>;
410 };
411 };
412
413 sram_c1: sram@1d00000 {
414 compatible = "mmio-sram";
415 reg = <0x01d00000 0x40000>;
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0 0x01d00000 0x40000>;
419
420 ve_sram: sram-section@0 {
421 compatible = "allwinner,sun50i-a64-sram-c1",
422 "allwinner,sun4i-a10-sram-c1";
423 reg = <0x000000 0x40000>;
424 };
425 };
426 };
427
428 dma: dma-controller@1c02000 {
429 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>;
434 dma-requests = <27>;
435 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>;
437 };
438
439 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = "tcon-data-clock";
447 #clock-cells = <0>;
448 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", "lvds";
450
451 ports {
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 tcon0_in: port@0 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <0>;
459
460 tcon0_in_mixer0: endpoint@0 {
461 reg = <0>;
462 remote-endpoint = <&mixer0_out_tcon0>;
463 };
464
465 tcon0_in_mixer1: endpoint@1 {
466 reg = <1>;
467 remote-endpoint = <&mixer1_out_tcon0>;
468 };
469 };
470
471 tcon0_out: port@1 {
472 #address-cells = <1>;
473 #size-cells = <0>;
474 reg = <1>;
475
476 tcon0_out_dsi: endpoint@1 {
477 reg = <1>;
478 remote-endpoint = <&dsi_in_tcon0>;
479 allwinner,tcon-channel = <1>;
480 };
481 };
482 };
483 };
484
485 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd";
494
495 ports {
496 #address-cells = <1>;
497 #size-cells = <0>;
498
499 tcon1_in: port@0 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <0>;
503
504 tcon1_in_mixer0: endpoint@0 {
505 reg = <0>;
506 remote-endpoint = <&mixer0_out_tcon1>;
507 };
508
509 tcon1_in_mixer1: endpoint@1 {
510 reg = <1>;
511 remote-endpoint = <&mixer1_out_tcon1>;
512 };
513 };
514
515 tcon1_out: port@1 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <1>;
519
520 tcon1_out_hdmi: endpoint@1 {
521 reg = <1>;
522 remote-endpoint = <&hdmi_in_tcon1>;
523 };
524 };
525 };
526 };
527
528 video-codec@1c0e000 {
529 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_sram 1>;
537 };
538
539 mmc0: mmc@1c0f000 {
540 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb";
546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <150000000>;
548 status = "disabled";
549 #address-cells = <1>;
550 #size-cells = <0>;
551 };
552
553 mmc1: mmc@1c10000 {
554 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb";
560 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <150000000>;
562 status = "disabled";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 };
566
567 mmc2: mmc@1c11000 {
568 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb";
574 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <150000000>;
576 status = "disabled";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 };
580
581 sid: eeprom@1c14000 {
582 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400>;
584 #address-cells = <1>;
585 #size-cells = <1>;
586
587 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x8>;
589 };
590 };
591
592 crypto: crypto@1c15000 {
593 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS_CE>;
599 };
600
601 msgbox: mailbox@1c17000 {
602 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>;
609 };
610
611 usb_otg: usb@1c19000 {
612 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc";
618 phys = <&usbphy 0>;
619 phy-names = "usb";
620 extcon = <&usbphy 0>;
621 dr_mode = "otg";
622 status = "disabled";
623 };
624
625 usbphy: phy@1c19400 {
626 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl",
631 "pmu0",
632 "pmu1";
633 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_phy",
636 "usb1_phy";
637 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_reset",
640 "usb1_reset";
641 status = "disabled";
642 #phy-cells = <1>;
643 };
644
645 ehci0: usb@1c1a000 {
646 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>;
655 phy-names = "usb";
656 status = "disabled";
657 };
658
659 ohci0: usb@1c1a400 {
660 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>;
667 phy-names = "usb";
668 status = "disabled";
669 };
670
671 ehci1: usb@1c1b000 {
672 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>;
681 phy-names = "usb";
682 status = "disabled";
683 };
684
685 ohci1: usb@1c1b400 {
686 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>;
693 phy-names = "usb";
694 status = "disabled";
695 };
696
697 ccu: clock@1c20000 {
698 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
701 clock-names = "hosc", "losc";
702 #clock-cells = <1>;
703 #reset-cells = <1>;
704 };
705
706 pio: pinctrl@1c20800 {
707 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
714 <&rtc CLK_OSC32K>;
715 clock-names = "apb", "hosc", "losc";
716 gpio-controller;
717 #gpio-cells = <3>;
718 interrupt-controller;
719 #interrupt-cells = <3>;
720
721 /omit-if-no-ref/
722 aif2_pins: aif2-pins {
723 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "aif2";
725 };
726
727 /omit-if-no-ref/
728 aif3_pins: aif3-pins {
729 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "aif3";
731 };
732
733 csi_pins: csi-pins {
734 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "csi";
737 };
738
739 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1";
742 function = "csi";
743 };
744
745 i2c0_pins: i2c0-pins {
746 pins = "PH0", "PH1";
747 function = "i2c0";
748 };
749
750 i2c1_pins: i2c1-pins {
751 pins = "PH2", "PH3";
752 function = "i2c1";
753 };
754
755 i2c2_pins: i2c2-pins {
756 pins = "PE14", "PE15";
757 function = "i2c2";
758 };
759
760 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", "PD11", "PD12", "PD13",
765 "PD14", "PD15", "PD16", "PD17",
766 "PD18", "PD19", "PD20", "PD21";
767 function = "lcd0";
768 };
769
770 mmc0_pins: mmc0-pins {
771 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", "PF5";
773 function = "mmc0";
774 drive-strength = <30>;
775 bias-pull-up;
776 };
777
778 mmc1_pins: mmc1-pins {
779 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", "PG5";
781 function = "mmc1";
782 drive-strength = <30>;
783 bias-pull-up;
784 };
785
786 mmc2_pins: mmc2-pins {
787 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10","PC11", "PC12", "PC13",
789 "PC14", "PC15", "PC16";
790 function = "mmc2";
791 drive-strength = <30>;
792 bias-pull-up;
793 };
794
795 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1";
797 function = "mmc2";
798 drive-strength = <30>;
799 bias-pull-up;
800 };
801
802 pwm_pin: pwm-pin {
803 pins = "PD22";
804 function = "pwm";
805 };
806
807 rmii_pins: rmii-pins {
808 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "emac";
811 drive-strength = <40>;
812 };
813
814 rgmii_pins: rgmii-pins {
815 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "emac";
819 drive-strength = <40>;
820 };
821
822 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8";
824 function = "spdif";
825 };
826
827 spi0_pins: spi0-pins {
828 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "spi0";
830 };
831
832 spi1_pins: spi1-pins {
833 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "spi1";
835 };
836
837 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", "PB9";
839 function = "uart0";
840 };
841
842 uart1_pins: uart1-pins {
843 pins = "PG6", "PG7";
844 function = "uart1";
845 };
846
847 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", "PG9";
849 function = "uart1";
850 };
851
852 uart2_pins: uart2-pins {
853 pins = "PB0", "PB1";
854 function = "uart2";
855 };
856
857 uart3_pins: uart3-pins {
858 pins = "PD0", "PD1";
859 function = "uart3";
860 };
861
862 uart4_pins: uart4-pins {
863 pins = "PD2", "PD3";
864 function = "uart4";
865 };
866
867 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", "PD5";
869 function = "uart4";
870 };
871 };
872
873 timer@1c20c00 {
874 compatible = "allwinner,sun50i-a64-timer",
875 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>;
880 };
881
882 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>;
888 };
889
890 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0>;
892 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", "spdif";
899 dmas = <&dma 2>;
900 dma-names = "tx";
901 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled";
904 };
905
906 lradc: lradc@1c21800 {
907 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled";
913 };
914
915 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0>;
917 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled";
927 };
928
929 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0>;
931 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled";
941 };
942
943 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0>;
945 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled";
955 };
956
957 dai: dai@1c22c00 {
958 #sound-dai-cells = <0>;
959 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx";
967 status = "disabled";
968 };
969
970 codec: codec@1c22e00 {
971 #sound-dai-cells = <1>;
972 compatible = "allwinner,sun50i-a64-codec",
973 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", "mod";
978 status = "disabled";
979 };
980
981 ths: thermal-sensor@1c25000 {
982 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells = <1>;
991 };
992
993 uart0: serial@1c28000 {
994 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>;
998 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled";
1002 };
1003
1004 uart1: serial@1c28400 {
1005 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>;
1009 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled";
1013 };
1014
1015 uart2: serial@1c28800 {
1016 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>;
1020 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled";
1024 };
1025
1026 uart3: serial@1c28c00 {
1027 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>;
1031 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled";
1035 };
1036
1037 uart4: serial@1c29000 {
1038 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>;
1042 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled";
1046 };
1047
1048 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 };
1060
1061 i2c1: i2c@1c2b000 {
1062 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled";
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 };
1073
1074 i2c2: i2c@1c2b400 {
1075 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 };
1086
1087 spi0: spi@1c68000 {
1088 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled";
1099 num-cs = <1>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 };
1103
1104 spi1: spi@1c69000 {
1105 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled";
1116 num-cs = <1>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 };
1120
1121 emac: ethernet@1c30000 {
1122 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>;
1124 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "macirq";
1127 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmaceth";
1131 status = "disabled";
1132
1133 mdio: mdio {
1134 compatible = "snps,dwmac-mdio";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 };
1138 };
1139
1140 mali: gpu@1c40000 {
1141 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp",
1151 "gpmmu",
1152 "pp0",
1153 "ppmmu0",
1154 "pp1",
1155 "ppmmu1",
1156 "pmu";
1157 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", "core";
1159 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = <&gpu_opp_table>;
1161 };
1162
1163 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller;
1171 #interrupt-cells = <3>;
1172 };
1173
1174 pwm: pwm@1c21400 {
1175 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>;
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>;
1182 status = "disabled";
1183 };
1184
1185 mbus: dram-controller@1c62000 {
1186 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1000>,
1188 <0x01c63000 0x1000>;
1189 reg-names = "mbus", "dram";
1190 clocks = <&ccu CLK_MBUS>,
1191 <&ccu CLK_DRAM>,
1192 <&ccu CLK_BUS_DRAM>;
1193 clock-names = "mbus", "dram", "bus";
1194 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>;
1196 #size-cells = <1>;
1197 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = <1>;
1199 };
1200
1201 csi: csi@1cb0000 {
1202 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pins>;
1212 status = "disabled";
1213 };
1214
1215 dsi: dsi@1ca0000 {
1216 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>;
1222 phy-names = "dphy";
1223 status = "disabled";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226
1227 port {
1228 dsi_in_tcon0: endpoint {
1229 remote-endpoint = <&tcon0_out_dsi>;
1230 };
1231 };
1232 };
1233
1234 dphy: d-phy@1ca1000 {
1235 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled";
1244 #phy-cells = <0>;
1245 };
1246
1247 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbus 9>;
1258 interconnect-names = "dma-mem";
1259 };
1260
1261 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1269 clock-names = "iahb", "isfr", "tmds", "cec";
1270 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl";
1272 phys = <&hdmi_phy>;
1273 phy-names = "phy";
1274 status = "disabled";
1275
1276 ports {
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279
1280 hdmi_in: port@0 {
1281 reg = <0>;
1282
1283 hdmi_in_tcon1: endpoint {
1284 remote-endpoint = <&tcon1_out_hdmi>;
1285 };
1286 };
1287
1288 hdmi_out: port@1 {
1289 reg = <1>;
1290 };
1291 };
1292 };
1293
1294 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy";
1302 #phy-cells = <0>;
1303 };
1304
1305 rtc: rtc@1f00000 {
1306 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>;
1314 #clock-cells = <1>;
1315 };
1316
1317 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller;
1321 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 };
1325
1326 r_ccu: clock@1f01400 {
1327 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1330 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>;
1333 #reset-cells = <1>;
1334 };
1335
1336 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4>;
1339 status = "disabled";
1340 };
1341
1342 r_i2c: i2c@1f02400 {
1343 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled";
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1352 };
1353
1354 r_ir: ir@1f02000 {
1355 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled";
1365 };
1366
1367 r_pwm: pwm@1f03800 {
1368 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>;
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>;
1375 status = "disabled";
1376 };
1377
1378 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", "hosc", "losc";
1385 gpio-controller;
1386 #gpio-cells = <3>;
1387 interrupt-controller;
1388 #interrupt-cells = <3>;
1389
1390 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", "PL9";
1392 function = "s_i2c";
1393 };
1394
1395 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11";
1397 function = "s_cir_rx";
1398 };
1399
1400 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10";
1402 function = "s_pwm";
1403 };
1404
1405 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", "PL1";
1407 function = "s_rsb";
1408 };
1409 };
1410
1411 r_rsb: rsb@1f03400 {
1412 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>;
1416 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>;
1418 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 };
1424 };
1425 };
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