1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC
4 *
5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10 / {
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu-map {
19 cluster0 {
20 core0 {
21 cpu = <&cpu_e00>;
22 };
23 core1 {
24 cpu = <&cpu_e01>;
25 };
26 };
27
28 cluster1 {
29 core0 {
30 cpu = <&cpu_p00>;
31 };
32 core1 {
33 cpu = <&cpu_p01>;
34 };
35 core2 {
36 cpu = <&cpu_p02>;
37 };
38 core3 {
39 cpu = <&cpu_p03>;
40 };
41 };
42
43 cluster2 {
44 core0 {
45 cpu = <&cpu_p10>;
46 };
47 core1 {
48 cpu = <&cpu_p11>;
49 };
50 core2 {
51 cpu = <&cpu_p12>;
52 };
53 core3 {
54 cpu = <&cpu_p13>;
55 };
56 };
57 };
58
59 cpu_e00: cpu@0 {
60 compatible = "apple,icestorm";
61 device_type = "cpu";
62 reg = <0x0 0x0>;
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
67 d-cache-size = <0x10000>;
68 operating-points-v2 = <&icestorm_opp>;
69 capacity-dmips-mhz = <714>;
70 performance-domains = <&cpufreq_e>;
71 };
72
73 cpu_e01: cpu@1 {
74 compatible = "apple,icestorm";
75 device_type = "cpu";
76 reg = <0x0 0x1>;
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0>; /* To be filled by loader */
79 next-level-cache = <&l2_cache_0>;
80 i-cache-size = <0x20000>;
81 d-cache-size = <0x10000>;
82 operating-points-v2 = <&icestorm_opp>;
83 capacity-dmips-mhz = <714>;
84 performance-domains = <&cpufreq_e>;
85 };
86
87 cpu_p00: cpu@10100 {
88 compatible = "apple,firestorm";
89 device_type = "cpu";
90 reg = <0x0 0x10100>;
91 enable-method = "spin-table";
92 cpu-release-addr = <0 0>; /* To be filled by loader */
93 next-level-cache = <&l2_cache_1>;
94 i-cache-size = <0x30000>;
95 d-cache-size = <0x20000>;
96 operating-points-v2 = <&firestorm_opp>;
97 capacity-dmips-mhz = <1024>;
98 performance-domains = <&cpufreq_p0>;
99 };
100
101 cpu_p01: cpu@10101 {
102 compatible = "apple,firestorm";
103 device_type = "cpu";
104 reg = <0x0 0x10101>;
105 enable-method = "spin-table";
106 cpu-release-addr = <0 0>; /* To be filled by loader */
107 next-level-cache = <&l2_cache_1>;
108 i-cache-size = <0x30000>;
109 d-cache-size = <0x20000>;
110 operating-points-v2 = <&firestorm_opp>;
111 capacity-dmips-mhz = <1024>;
112 performance-domains = <&cpufreq_p0>;
113 };
114
115 cpu_p02: cpu@10102 {
116 compatible = "apple,firestorm";
117 device_type = "cpu";
118 reg = <0x0 0x10102>;
119 enable-method = "spin-table";
120 cpu-release-addr = <0 0>; /* To be filled by loader */
121 next-level-cache = <&l2_cache_1>;
122 i-cache-size = <0x30000>;
123 d-cache-size = <0x20000>;
124 operating-points-v2 = <&firestorm_opp>;
125 capacity-dmips-mhz = <1024>;
126 performance-domains = <&cpufreq_p0>;
127 };
128
129 cpu_p03: cpu@10103 {
130 compatible = "apple,firestorm";
131 device_type = "cpu";
132 reg = <0x0 0x10103>;
133 enable-method = "spin-table";
134 cpu-release-addr = <0 0>; /* To be filled by loader */
135 next-level-cache = <&l2_cache_1>;
136 i-cache-size = <0x30000>;
137 d-cache-size = <0x20000>;
138 operating-points-v2 = <&firestorm_opp>;
139 capacity-dmips-mhz = <1024>;
140 performance-domains = <&cpufreq_p0>;
141 };
142
143 cpu_p10: cpu@10200 {
144 compatible = "apple,firestorm";
145 device_type = "cpu";
146 reg = <0x0 0x10200>;
147 enable-method = "spin-table";
148 cpu-release-addr = <0 0>; /* To be filled by loader */
149 next-level-cache = <&l2_cache_2>;
150 i-cache-size = <0x30000>;
151 d-cache-size = <0x20000>;
152 operating-points-v2 = <&firestorm_opp>;
153 capacity-dmips-mhz = <1024>;
154 performance-domains = <&cpufreq_p1>;
155 };
156
157 cpu_p11: cpu@10201 {
158 compatible = "apple,firestorm";
159 device_type = "cpu";
160 reg = <0x0 0x10201>;
161 enable-method = "spin-table";
162 cpu-release-addr = <0 0>; /* To be filled by loader */
163 next-level-cache = <&l2_cache_2>;
164 i-cache-size = <0x30000>;
165 d-cache-size = <0x20000>;
166 operating-points-v2 = <&firestorm_opp>;
167 capacity-dmips-mhz = <1024>;
168 performance-domains = <&cpufreq_p1>;
169 };
170
171 cpu_p12: cpu@10202 {
172 compatible = "apple,firestorm";
173 device_type = "cpu";
174 reg = <0x0 0x10202>;
175 enable-method = "spin-table";
176 cpu-release-addr = <0 0>; /* To be filled by loader */
177 next-level-cache = <&l2_cache_2>;
178 i-cache-size = <0x30000>;
179 d-cache-size = <0x20000>;
180 operating-points-v2 = <&firestorm_opp>;
181 capacity-dmips-mhz = <1024>;
182 performance-domains = <&cpufreq_p1>;
183 };
184
185 cpu_p13: cpu@10203 {
186 compatible = "apple,firestorm";
187 device_type = "cpu";
188 reg = <0x0 0x10203>;
189 enable-method = "spin-table";
190 cpu-release-addr = <0 0>; /* To be filled by loader */
191 next-level-cache = <&l2_cache_2>;
192 i-cache-size = <0x30000>;
193 d-cache-size = <0x20000>;
194 operating-points-v2 = <&firestorm_opp>;
195 capacity-dmips-mhz = <1024>;
196 performance-domains = <&cpufreq_p1>;
197 };
198
199 l2_cache_0: l2-cache-0 {
200 compatible = "cache";
201 cache-level = <2>;
202 cache-unified;
203 cache-size = <0x400000>;
204 };
205
206 l2_cache_1: l2-cache-1 {
207 compatible = "cache";
208 cache-level = <2>;
209 cache-unified;
210 cache-size = <0xc00000>;
211 };
212
213 l2_cache_2: l2-cache-2 {
214 compatible = "cache";
215 cache-level = <2>;
216 cache-unified;
217 cache-size = <0xc00000>;
218 };
219 };
220
221 icestorm_opp: opp-table-0 {
222 compatible = "operating-points-v2";
223
224 opp01 {
225 opp-hz = /bits/ 64 <600000000>;
226 opp-level = <1>;
227 clock-latency-ns = <7500>;
228 };
229 opp02 {
230 opp-hz = /bits/ 64 <972000000>;
231 opp-level = <2>;
232 clock-latency-ns = <23000>;
233 };
234 opp03 {
235 opp-hz = /bits/ 64 <1332000000>;
236 opp-level = <3>;
237 clock-latency-ns = <29000>;
238 };
239 opp04 {
240 opp-hz = /bits/ 64 <1704000000>;
241 opp-level = <4>;
242 clock-latency-ns = <40000>;
243 };
244 opp05 {
245 opp-hz = /bits/ 64 <2064000000>;
246 opp-level = <5>;
247 clock-latency-ns = <50000>;
248 };
249 };
250
251 firestorm_opp: opp-table-1 {
252 compatible = "operating-points-v2";
253
254 opp01 {
255 opp-hz = /bits/ 64 <600000000>;
256 opp-level = <1>;
257 clock-latency-ns = <8000>;
258 };
259 opp02 {
260 opp-hz = /bits/ 64 <828000000>;
261 opp-level = <2>;
262 clock-latency-ns = <18000>;
263 };
264 opp03 {
265 opp-hz = /bits/ 64 <1056000000>;
266 opp-level = <3>;
267 clock-latency-ns = <19000>;
268 };
269 opp04 {
270 opp-hz = /bits/ 64 <1296000000>;
271 opp-level = <4>;
272 clock-latency-ns = <23000>;
273 };
274 opp05 {
275 opp-hz = /bits/ 64 <1524000000>;
276 opp-level = <5>;
277 clock-latency-ns = <24000>;
278 };
279 opp06 {
280 opp-hz = /bits/ 64 <1752000000>;
281 opp-level = <6>;
282 clock-latency-ns = <28000>;
283 };
284 opp07 {
285 opp-hz = /bits/ 64 <1980000000>;
286 opp-level = <7>;
287 clock-latency-ns = <31000>;
288 };
289 opp08 {
290 opp-hz = /bits/ 64 <2208000000>;
291 opp-level = <8>;
292 clock-latency-ns = <45000>;
293 };
294 opp09 {
295 opp-hz = /bits/ 64 <2448000000>;
296 opp-level = <9>;
297 clock-latency-ns = <49000>;
298 };
299 opp10 {
300 opp-hz = /bits/ 64 <2676000000>;
301 opp-level = <10>;
302 clock-latency-ns = <53000>;
303 };
304 opp11 {
305 opp-hz = /bits/ 64 <2904000000>;
306 opp-level = <11>;
307 clock-latency-ns = <56000>;
308 };
309 opp12 {
310 opp-hz = /bits/ 64 <3036000000>;
311 opp-level = <12>;
312 clock-latency-ns = <56000>;
313 };
314 /* Not available until CPU deep sleep is implemented
315 opp13 {
316 opp-hz = /bits/ 64 <3132000000>;
317 opp-level = <13>;
318 clock-latency-ns = <56000>;
319 turbo-mode;
320 };
321 opp14 {
322 opp-hz = /bits/ 64 <3168000000>;
323 opp-level = <14>;
324 clock-latency-ns = <56000>;
325 turbo-mode;
326 };
327 opp15 {
328 opp-hz = /bits/ 64 <3228000000>;
329 opp-level = <15>;
330 clock-latency-ns = <56000>;
331 turbo-mode;
332 };
333 */
334 };
335
336 pmu-e {
337 compatible = "apple,icestorm-pmu";
338 interrupt-parent = <&aic>;
339 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
340 };
341
342 pmu-p {
343 compatible = "apple,firestorm-pmu";
344 interrupt-parent = <&aic>;
345 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
346 };
347
348 timer {
349 compatible = "arm,armv8-timer";
350 interrupt-parent = <&aic>;
351 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
352 interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
353 <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
354 <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
355 <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
356 };
357
358 clkref: clock-ref {
359 compatible = "fixed-clock";
360 #clock-cells = <0>;
361 clock-frequency = <24000000>;
362 clock-output-names = "clkref";
363 };
364
365 /*
366 * This is a fabulated representation of the input clock
367 * to NCO since we don't know the true clock tree.
368 */
369 nco_clkref: clock-ref-nco {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 clock-output-names = "nco_ref";
373 };
374 };
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