1 /*
2 * ARM Juno Platform motherboard peripherals
3 *
4 * Copyright (c) 2013-2014 ARM Ltd
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 *
8 */
9
10 / {
11 mb_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
16 };
17
18 mb_clk25mhz: clock-25000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <25000000>;
22 clock-output-names = "juno_mb:clk25mhz";
23 };
24
25 v2m_refclk1mhz: clock-1000000 {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <1000000>;
29 clock-output-names = "juno_mb:refclk1mhz";
30 };
31
32 v2m_refclk32khz: clock-32768 {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <32768>;
36 clock-output-names = "juno_mb:refclk32khz";
37 };
38
39 mb_fixed_3v3: regulator-3v3 {
40 compatible = "regulator-fixed";
41 regulator-name = "MCC_SB_3V3";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49
50 power-button {
51 debounce-interval = <50>;
52 wakeup-source;
53 linux,code = <116>;
54 label = "POWER";
55 gpios = <&iofpga_gpio0 0 0x4>;
56 };
57 home-button {
58 debounce-interval = <50>;
59 wakeup-source;
60 linux,code = <102>;
61 label = "HOME";
62 gpios = <&iofpga_gpio0 1 0x4>;
63 };
64 rlock-button {
65 debounce-interval = <50>;
66 wakeup-source;
67 linux,code = <152>;
68 label = "RLOCK";
69 gpios = <&iofpga_gpio0 2 0x4>;
70 };
71 vol-up-button {
72 debounce-interval = <50>;
73 wakeup-source;
74 linux,code = <115>;
75 label = "VOL+";
76 gpios = <&iofpga_gpio0 3 0x4>;
77 };
78 vol-down-button {
79 debounce-interval = <50>;
80 wakeup-source;
81 linux,code = <114>;
82 label = "VOL-";
83 gpios = <&iofpga_gpio0 4 0x4>;
84 };
85 nmi-button {
86 debounce-interval = <50>;
87 wakeup-source;
88 linux,code = <99>;
89 label = "NMI";
90 gpios = <&iofpga_gpio0 5 0x4>;
91 };
92 };
93
94 bus@8000000 {
95 compatible = "simple-bus";
96 #address-cells = <2>;
97 #size-cells = <1>;
98 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
99
100 motherboard-bus@8000000 {
101 compatible = "arm,vexpress,v2p-p1", "simple-bus";
102 #address-cells = <2>; /* SMB chipselect number and offset */
103 #size-cells = <1>;
104 ranges = <0 0 0 0x08000000 0x04000000>,
105 <1 0 0 0x14000000 0x04000000>,
106 <2 0 0 0x18000000 0x04000000>,
107 <3 0 0 0x1c000000 0x04000000>,
108 <4 0 0 0x0c000000 0x04000000>,
109 <5 0 0 0x10000000 0x04000000>;
110 arm,hbi = <0x252>;
111 arm,vexpress,site = <0>;
112
113 flash@0 {
114 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
115 compatible = "arm,vexpress-flash", "cfi-flash";
116 reg = <0 0x00000000 0x04000000>;
117 bank-width = <4>;
118 /*
119 * Unfortunately, accessing the flash disturbs
120 * the CPU idle states (suspend) and CPU
121 * hotplug of the platform. For this reason,
122 * flash hardware access is disabled by default.
123 */
124 status = "disabled";
125 partitions {
126 compatible = "arm,arm-firmware-suite";
127 };
128 };
129
130 ethernet@200000000 {
131 compatible = "smsc,lan9118", "smsc,lan9115";
132 reg = <2 0x00000000 0x10000>;
133 interrupts = <3>;
134 phy-mode = "mii";
135 reg-io-width = <4>;
136 smsc,irq-active-high;
137 smsc,irq-push-pull;
138 clocks = <&mb_clk25mhz>;
139 vdd33a-supply = <&mb_fixed_3v3>;
140 vddvario-supply = <&mb_fixed_3v3>;
141 };
142
143 iofpga-bus@300000000 {
144 compatible = "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 3 0 0x200000>;
148
149 v2m_sysctl: sysctl@20000 {
150 compatible = "arm,sp810", "arm,primecell";
151 reg = <0x020000 0x1000>;
152 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
153 clock-names = "refclk", "timclk", "apb_pclk";
154 #clock-cells = <1>;
155 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
157 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
158 };
159
160 apbregs@10000 {
161 compatible = "arm,juno-fpga-apb-regs",
162 "syscon", "simple-mfd";
163 reg = <0x010000 0x1000>;
164 ranges = <0x0 0x10000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <1>;
167
168 led@8,0 {
169 compatible = "register-bit-led";
170 reg = <0x08 0x04>;
171 offset = <0x08>;
172 mask = <0x01>;
173 label = "vexpress:0";
174 linux,default-trigger = "heartbeat";
175 default-state = "on";
176 };
177 led@8,1 {
178 compatible = "register-bit-led";
179 reg = <0x08 0x04>;
180 offset = <0x08>;
181 mask = <0x02>;
182 label = "vexpress:1";
183 linux,default-trigger = "mmc0";
184 default-state = "off";
185 };
186 led@8,2 {
187 compatible = "register-bit-led";
188 reg = <0x08 0x04>;
189 offset = <0x08>;
190 mask = <0x04>;
191 label = "vexpress:2";
192 linux,default-trigger = "cpu0";
193 default-state = "off";
194 };
195 led@8,3 {
196 compatible = "register-bit-led";
197 reg = <0x08 0x04>;
198 offset = <0x08>;
199 mask = <0x08>;
200 label = "vexpress:3";
201 linux,default-trigger = "cpu1";
202 default-state = "off";
203 };
204 led@8,4 {
205 compatible = "register-bit-led";
206 reg = <0x08 0x04>;
207 offset = <0x08>;
208 mask = <0x10>;
209 label = "vexpress:4";
210 linux,default-trigger = "cpu2";
211 default-state = "off";
212 };
213 led@8,5 {
214 compatible = "register-bit-led";
215 reg = <0x08 0x04>;
216 offset = <0x08>;
217 mask = <0x20>;
218 label = "vexpress:5";
219 linux,default-trigger = "cpu3";
220 default-state = "off";
221 };
222 led@8,6 {
223 compatible = "register-bit-led";
224 reg = <0x08 0x04>;
225 offset = <0x08>;
226 mask = <0x40>;
227 label = "vexpress:6";
228 default-state = "off";
229 };
230 led@8,7 {
231 compatible = "register-bit-led";
232 reg = <0x08 0x04>;
233 offset = <0x08>;
234 mask = <0x80>;
235 label = "vexpress:7";
236 default-state = "off";
237 };
238 };
239
240 mmc@50000 {
241 compatible = "arm,pl180", "arm,primecell";
242 reg = <0x050000 0x1000>;
243 interrupts = <5>;
244 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
245 wp-gpios = <&v2m_mmc_gpios 1 0>; */
246 max-frequency = <12000000>;
247 vmmc-supply = <&mb_fixed_3v3>;
248 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
249 clock-names = "mclk", "apb_pclk";
250 };
251
252 kmi@60000 {
253 compatible = "arm,pl050", "arm,primecell";
254 reg = <0x060000 0x1000>;
255 interrupts = <8>;
256 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
257 clock-names = "KMIREFCLK", "apb_pclk";
258 };
259
260 kmi@70000 {
261 compatible = "arm,pl050", "arm,primecell";
262 reg = <0x070000 0x1000>;
263 interrupts = <8>;
264 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
265 clock-names = "KMIREFCLK", "apb_pclk";
266 };
267
268 watchdog@f0000 {
269 compatible = "arm,sp805", "arm,primecell";
270 reg = <0x0f0000 0x10000>;
271 interrupts = <7>;
272 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
273 clock-names = "wdog_clk", "apb_pclk";
274 };
275
276 v2m_timer01: timer@110000 {
277 compatible = "arm,sp804", "arm,primecell";
278 reg = <0x110000 0x10000>;
279 interrupts = <9>;
280 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
281 clock-names = "timclken1", "timclken2", "apb_pclk";
282 };
283
284 v2m_timer23: timer@120000 {
285 compatible = "arm,sp804", "arm,primecell";
286 reg = <0x120000 0x10000>;
287 interrupts = <9>;
288 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
289 clock-names = "timclken1", "timclken2", "apb_pclk";
290 };
291
292 rtc@170000 {
293 compatible = "arm,pl031", "arm,primecell";
294 reg = <0x170000 0x10000>;
295 interrupts = <0>;
296 clocks = <&soc_smc50mhz>;
297 clock-names = "apb_pclk";
298 };
299
300 iofpga_gpio0: gpio@1d0000 {
301 compatible = "arm,pl061", "arm,primecell";
302 reg = <0x1d0000 0x1000>;
303 interrupts = <6>;
304 clocks = <&soc_smc50mhz>;
305 clock-names = "apb_pclk";
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311 };
312 };
313 };
314 };
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