1 /*
2 * ARM Ltd. Juno Platform
3 *
4 * Copyright (c) 2015 ARM Ltd.
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
15
16 / {
17 model = "ARM Juno development board (r1)";
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 serial0 = &soc_uart0;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 };
30
31 psci {
32 compatible = "arm,psci-0.2";
33 method = "smc";
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 cpu-map {
41 cluster0 {
42 core0 {
43 cpu = <&A57_0>;
44 };
45 core1 {
46 cpu = <&A57_1>;
47 };
48 };
49
50 cluster1 {
51 core0 {
52 cpu = <&A53_0>;
53 };
54 core1 {
55 cpu = <&A53_1>;
56 };
57 core2 {
58 cpu = <&A53_2>;
59 };
60 core3 {
61 cpu = <&A53_3>;
62 };
63 };
64 };
65
66 idle-states {
67 entry-method = "psci";
68
69 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = "arm,idle-state";
71 arm,psci-suspend-param = <0x0010000>;
72 local-timer-stop;
73 entry-latency-us = <300>;
74 exit-latency-us = <1200>;
75 min-residency-us = <2000>;
76 };
77
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = "arm,idle-state";
80 arm,psci-suspend-param = <0x1010000>;
81 local-timer-stop;
82 entry-latency-us = <400>;
83 exit-latency-us = <1200>;
84 min-residency-us = <2500>;
85 };
86 };
87
88 A57_0: cpu@0 {
89 compatible = "arm,cortex-a57";
90 reg = <0x0 0x0>;
91 device_type = "cpu";
92 enable-method = "psci";
93 i-cache-size = <0xc000>;
94 i-cache-line-size = <64>;
95 i-cache-sets = <256>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
98 d-cache-sets = <256>;
99 next-level-cache = <&A57_L2>;
100 clocks = <&scpi_dvfs 0>;
101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = <1024>;
103 };
104
105 A57_1: cpu@1 {
106 compatible = "arm,cortex-a57";
107 reg = <0x0 0x1>;
108 device_type = "cpu";
109 enable-method = "psci";
110 i-cache-size = <0xc000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <0x8000>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <256>;
116 next-level-cache = <&A57_L2>;
117 clocks = <&scpi_dvfs 0>;
118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119 capacity-dmips-mhz = <1024>;
120 };
121
122 A53_0: cpu@100 {
123 compatible = "arm,cortex-a53";
124 reg = <0x0 0x100>;
125 device_type = "cpu";
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 clocks = <&scpi_dvfs 1>;
135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136 capacity-dmips-mhz = <578>;
137 };
138
139 A53_1: cpu@101 {
140 compatible = "arm,cortex-a53";
141 reg = <0x0 0x101>;
142 device_type = "cpu";
143 enable-method = "psci";
144 i-cache-size = <0x8000>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <0x8000>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <128>;
150 next-level-cache = <&A53_L2>;
151 clocks = <&scpi_dvfs 1>;
152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
153 capacity-dmips-mhz = <578>;
154 };
155
156 A53_2: cpu@102 {
157 compatible = "arm,cortex-a53";
158 reg = <0x0 0x102>;
159 device_type = "cpu";
160 enable-method = "psci";
161 i-cache-size = <0x8000>;
162 i-cache-line-size = <64>;
163 i-cache-sets = <256>;
164 d-cache-size = <0x8000>;
165 d-cache-line-size = <64>;
166 d-cache-sets = <128>;
167 next-level-cache = <&A53_L2>;
168 clocks = <&scpi_dvfs 1>;
169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
170 capacity-dmips-mhz = <578>;
171 };
172
173 A53_3: cpu@103 {
174 compatible = "arm,cortex-a53";
175 reg = <0x0 0x103>;
176 device_type = "cpu";
177 enable-method = "psci";
178 i-cache-size = <0x8000>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <0x8000>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <128>;
184 next-level-cache = <&A53_L2>;
185 clocks = <&scpi_dvfs 1>;
186 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
187 capacity-dmips-mhz = <578>;
188 };
189
190 A57_L2: l2-cache0 {
191 compatible = "cache";
192 cache-unified;
193 cache-size = <0x200000>;
194 cache-line-size = <64>;
195 cache-sets = <2048>;
196 cache-level = <2>;
197 };
198
199 A53_L2: l2-cache1 {
200 compatible = "cache";
201 cache-unified;
202 cache-size = <0x100000>;
203 cache-line-size = <64>;
204 cache-sets = <1024>;
205 cache-level = <2>;
206 };
207 };
208
209 pmu-a57 {
210 compatible = "arm,cortex-a57-pmu";
211 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-affinity = <&A57_0>,
214 <&A57_1>;
215 };
216
217 pmu-a53 {
218 compatible = "arm,cortex-a53-pmu";
219 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-affinity = <&A53_0>,
224 <&A53_1>,
225 <&A53_2>,
226 <&A53_3>;
227 };
228 };
229
230 &memtimer {
231 status = "okay";
232 };
233
234 &pcie_ctlr {
235 status = "okay";
236 };
237
238 &smmu_pcie {
239 status = "okay";
240 };
241
242 &etm0 {
243 cpu = <&A57_0>;
244 };
245
246 &etm1 {
247 cpu = <&A57_1>;
248 };
249
250 &etm2 {
251 cpu = <&A53_0>;
252 };
253
254 &etm3 {
255 cpu = <&A53_1>;
256 };
257
258 &etm4 {
259 cpu = <&A53_2>;
260 };
261
262 &etm5 {
263 cpu = <&A53_3>;
264 };
265
266 &big_cluster_thermal_zone {
267 status = "okay";
268 };
269
270 &little_cluster_thermal_zone {
271 status = "okay";
272 };
273
274 &gpu0_thermal_zone {
275 status = "okay";
276 };
277
278 &gpu1_thermal_zone {
279 status = "okay";
280 };
281
282 &etf0_out_port {
283 remote-endpoint = <&csys2_funnel_in_port0>;
284 };
285
286 &replicator_in_port0 {
287 remote-endpoint = <&csys2_funnel_out_port>;
288 };
289
290 &csys1_funnel_in_port0 {
291 remote-endpoint = <&stm_out_port>;
292 };
293
294 &stm_out_port {
295 remote-endpoint = <&csys1_funnel_in_port0>;
296 };
297
298 &cpu_debug0 {
299 cpu = <&A57_0>;
300 };
301
302 &cpu_debug1 {
303 cpu = <&A57_1>;
304 };
305
306 &cpu_debug2 {
307 cpu = <&A53_0>;
308 };
309
310 &cpu_debug3 {
311 cpu = <&A53_1>;
312 };
313
314 &cpu_debug4 {
315 cpu = <&A53_2>;
316 };
317
318 &cpu_debug5 {
319 cpu = <&A53_3>;
320 };
321
322 &cti0 {
323 cpu = <&A57_0>;
324 };
325
326 &cti1 {
327 cpu = <&A57_1>;
328 };
329
330 &cti2 {
331 cpu = <&A53_0>;
332 };
333
334 &cti3 {
335 cpu = <&A53_1>;
336 };
337
338 &cti4 {
339 cpu = <&A53_2>;
340 };
341
342 &cti5 {
343 cpu = <&A53_3>;
344 };
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