1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
7
8 /dts-v1/;
9
10 / {
11 interrupt-parent = <&gic>;
12
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu0: cpu@0 {
29 device_type = "cpu";
30 compatible = "brcm,brahma-b53";
31 reg = <0x0>;
32 enable-method = "spin-table";
33 cpu-release-addr = <0x0 0xfff8>;
34 next-level-cache = <&l2>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "brcm,brahma-b53";
40 reg = <0x1>;
41 enable-method = "spin-table";
42 cpu-release-addr = <0x0 0xfff8>;
43 next-level-cache = <&l2>;
44 };
45
46 cpu2: cpu@2 {
47 device_type = "cpu";
48 compatible = "brcm,brahma-b53";
49 reg = <0x2>;
50 enable-method = "spin-table";
51 cpu-release-addr = <0x0 0xfff8>;
52 next-level-cache = <&l2>;
53 };
54
55 cpu3: cpu@3 {
56 device_type = "cpu";
57 compatible = "brcm,brahma-b53";
58 reg = <0x3>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0xfff8>;
61 next-level-cache = <&l2>;
62 };
63
64 l2: l2-cache0 {
65 compatible = "cache";
66 cache-level = <2>;
67 cache-unified;
68 };
69 };
70
71 axi@81000000 {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0x00 0x00 0x81000000 0x4000>;
76
77 gic: interrupt-controller@1000 {
78 compatible = "arm,gic-400";
79 #interrupt-cells = <3>;
80 #address-cells = <0>;
81 interrupt-controller;
82 reg = <0x1000 0x1000>,
83 <0x2000 0x2000>;
84 };
85 };
86
87 timer {
88 compatible = "arm,armv8-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 };
94
95 pmu {
96 compatible = "arm,cortex-a53-pmu";
97 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
102 };
103
104 clocks {
105 periph_clk: periph_clk {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <50000000>;
109 clock-output-names = "periph";
110 };
111
112 hsspi_pll: hsspi-pll {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <400000000>;
116 };
117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges = <0x00 0x00 0x80000000 0x281000>;
124
125 enet: ethernet@2000 {
126 compatible = "brcm,bcm4908-enet";
127 reg = <0x2000 0x1000>;
128
129 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "rx", "tx";
132 };
133
134 usb_phy: usb-phy@c200 {
135 compatible = "brcm,bcm4908-usb-phy";
136 reg = <0xc200 0x100>;
137 reg-names = "ctrl";
138 power-domains = <&pmb BCM_PMB_HOST_USB>;
139 dr_mode = "host";
140 brcm,has-xhci;
141 brcm,has-eohci;
142 #phy-cells = <1>;
143 status = "disabled";
144 };
145
146 ehci: usb@c300 {
147 compatible = "generic-ehci";
148 reg = <0xc300 0x100>;
149 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
150 phys = <&usb_phy PHY_TYPE_USB2>;
151 status = "disabled";
152
153 #address-cells = <1>;
154 #size-cells = <0>;
155
156 ehci_port1: port@1 {
157 reg = <1>;
158 #trigger-source-cells = <0>;
159 };
160
161 ehci_port2: port@2 {
162 reg = <2>;
163 #trigger-source-cells = <0>;
164 };
165 };
166
167 ohci: usb@c400 {
168 compatible = "generic-ohci";
169 reg = <0xc400 0x100>;
170 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
171 phys = <&usb_phy PHY_TYPE_USB2>;
172 status = "disabled";
173
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 ohci_port1: port@1 {
178 reg = <1>;
179 #trigger-source-cells = <0>;
180 };
181
182 ohci_port2: port@2 {
183 reg = <2>;
184 #trigger-source-cells = <0>;
185 };
186 };
187
188 xhci: usb@d000 {
189 compatible = "generic-xhci";
190 reg = <0xd000 0x8c8>;
191 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
192 phys = <&usb_phy PHY_TYPE_USB3>;
193 status = "disabled";
194
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 xhci_port1: port@1 {
199 reg = <1>;
200 #trigger-source-cells = <0>;
201 };
202
203 xhci_port2: port@2 {
204 reg = <2>;
205 #trigger-source-cells = <0>;
206 };
207 };
208
209 bus@80000 {
210 compatible = "simple-bus";
211 #size-cells = <1>;
212 #address-cells = <1>;
213 ranges = <0 0x80000 0x50000>;
214
215 ethernet-switch@0 {
216 compatible = "brcm,bcm4908-switch";
217 reg = <0x0 0x40000>,
218 <0x40000 0x110>,
219 <0x40340 0x30>,
220 <0x40380 0x30>,
221 <0x40600 0x34>,
222 <0x40800 0x208>;
223 reg-names = "core", "reg", "intrl2_0",
224 "intrl2_1", "fcb", "acb";
225 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
227 brcm,num-gphy = <5>;
228 brcm,num-rgmii-ports = <2>;
229
230 ports: ports {
231 #address-cells = <1>;
232 #size-cells = <0>;
233
234 port@0 {
235 reg = <0>;
236 phy-mode = "internal";
237 phy-handle = <&phy8>;
238 };
239
240 port@1 {
241 reg = <1>;
242 phy-mode = "internal";
243 phy-handle = <&phy9>;
244 };
245
246 port@2 {
247 reg = <2>;
248 phy-mode = "internal";
249 phy-handle = <&phy10>;
250 };
251
252 port@3 {
253 reg = <3>;
254 phy-mode = "internal";
255 phy-handle = <&phy11>;
256 };
257
258 port@8 {
259 reg = <8>;
260 phy-mode = "internal";
261 ethernet = <&enet>;
262
263 fixed-link {
264 speed = <1000>;
265 full-duplex;
266 };
267 };
268 };
269 };
270
271 mdio: mdio@405c0 {
272 compatible = "brcm,unimac-mdio";
273 reg = <0x405c0 0x8>;
274 reg-names = "mdio";
275 #size-cells = <0>;
276 #address-cells = <1>;
277
278 phy8: ethernet-phy@8 {
279 reg = <8>;
280 };
281
282 phy9: ethernet-phy@9 {
283 reg = <9>;
284 };
285
286 phy10: ethernet-phy@a {
287 reg = <10>;
288 };
289
290 phy11: ethernet-phy@b {
291 reg = <11>;
292 };
293
294 phy12: ethernet-phy@c {
295 reg = <12>;
296 };
297 };
298 };
299
300 procmon: bus@280000 {
301 compatible = "simple-bus";
302 reg = <0x280000 0x1000>;
303 ranges;
304
305 #address-cells = <1>;
306 #size-cells = <1>;
307
308 pmb: power-controller@2800c0 {
309 compatible = "brcm,bcm4908-pmb";
310 reg = <0x2800c0 0x40>;
311 #power-domain-cells = <1>;
312 };
313 };
314 };
315
316 bus@ff800000 {
317 compatible = "simple-bus";
318 #address-cells = <1>;
319 #size-cells = <1>;
320 ranges = <0x00 0x00 0xff800000 0x3000>;
321
322 twd: timer-mfd@400 {
323 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
324 reg = <0x400 0x4c>;
325 ranges = <0x0 0x400 0x4c>;
326
327 #address-cells = <1>;
328 #size-cells = <1>;
329
330 timer@0 {
331 compatible = "brcm,bcm63138-timer";
332 reg = <0x0 0x28>;
333 };
334
335 watchdog@28 {
336 compatible = "brcm,bcm6345-wdt";
337 reg = <0x28 0x8>;
338 };
339 };
340
341 gpio0: gpio-controller@500 {
342 compatible = "brcm,bcm6345-gpio";
343 reg-names = "dirout", "dat";
344 reg = <0x500 0x28>, <0x528 0x28>;
345
346 #gpio-cells = <2>;
347 gpio-controller;
348 };
349
350 pinctrl@560 {
351 compatible = "brcm,bcm4908-pinctrl";
352 reg = <0x560 0x10>;
353
354 pins_led_0_a: led_0-a-pins {
355 function = "led_0";
356 groups = "led_0_grp_a";
357 };
358
359 pins_led_1_a: led_1-a-pins {
360 function = "led_1";
361 groups = "led_1_grp_a";
362 };
363
364 pins_led_2_a: led_2-a-pins {
365 function = "led_2";
366 groups = "led_2_grp_a";
367 };
368
369 pins_led_3_a: led_3-a-pins {
370 function = "led_3";
371 groups = "led_3_grp_a";
372 };
373
374 pins_led_4_a: led_4-a-pins {
375 function = "led_4";
376 groups = "led_4_grp_a";
377 };
378
379 pins_led_5_a: led_5-a-pins {
380 function = "led_5";
381 groups = "led_5_grp_a";
382 };
383
384 pins_led_6_a: led_6-a-pins {
385 function = "led_6";
386 groups = "led_6_grp_a";
387 };
388
389 pins_led_7_a: led_7-a-pins {
390 function = "led_7";
391 groups = "led_7_grp_a";
392 };
393
394 pins_led_8_a: led_8-a-pins {
395 function = "led_8";
396 groups = "led_8_grp_a";
397 };
398
399 pins_led_9_a: led_9-a-pins {
400 function = "led_9";
401 groups = "led_9_grp_a";
402 };
403
404 pins_led_10_a: led_10-a-pins {
405 function = "led_10";
406 groups = "led_10_grp_a";
407 };
408
409 pins_led_11_a: led_11-a-pins {
410 function = "led_11";
411 groups = "led_11_grp_a";
412 };
413
414 pins_led_12_a: led_12-a-pins {
415 function = "led_12";
416 groups = "led_12_grp_a";
417 };
418
419 pins_led_13_a: led_13-a-pins {
420 function = "led_13";
421 groups = "led_13_grp_a";
422 };
423
424 pins_led_14_a: led_14-a-pins {
425 function = "led_14";
426 groups = "led_14_grp_a";
427 };
428
429 pins_led_15_a: led_15-a-pins {
430 function = "led_15";
431 groups = "led_15_grp_a";
432 };
433
434 pins_led_16_a: led_16-a-pins {
435 function = "led_16";
436 groups = "led_16_grp_a";
437 };
438
439 pins_led_17_a: led_17-a-pins {
440 function = "led_17";
441 groups = "led_17_grp_a";
442 };
443
444 pins_led_18_a: led_18-a-pins {
445 function = "led_18";
446 groups = "led_18_grp_a";
447 };
448
449 pins_led_19_a: led_19-a-pins {
450 function = "led_19";
451 groups = "led_19_grp_a";
452 };
453
454 pins_led_20_a: led_20-a-pins {
455 function = "led_20";
456 groups = "led_20_grp_a";
457 };
458
459 pins_led_21_a: led_21-a-pins {
460 function = "led_21";
461 groups = "led_21_grp_a";
462 };
463
464 pins_led_22_a: led_22-a-pins {
465 function = "led_22";
466 groups = "led_22_grp_a";
467 };
468
469 pins_led_23_a: led_23-a-pins {
470 function = "led_23";
471 groups = "led_23_grp_a";
472 };
473
474 pins_led_24_a: led_24-a-pins {
475 function = "led_24";
476 groups = "led_24_grp_a";
477 };
478
479 pins_led_25_a: led_25-a-pins {
480 function = "led_25";
481 groups = "led_25_grp_a";
482 };
483
484 pins_led_26_a: led_26-a-pins {
485 function = "led_26";
486 groups = "led_26_grp_a";
487 };
488
489 pins_led_27_a: led_27-a-pins {
490 function = "led_27";
491 groups = "led_27_grp_a";
492 };
493
494 pins_led_28_a: led_28-a-pins {
495 function = "led_28";
496 groups = "led_28_grp_a";
497 };
498
499 pins_led_29_a: led_29-a-pins {
500 function = "led_29";
501 groups = "led_29_grp_a";
502 };
503
504 pins_led_30_a: led_30-a-pins {
505 function = "led_30";
506 groups = "led_30_grp_a";
507 };
508
509 pins_led_31_a: led_31-a-pins {
510 function = "led_31";
511 groups = "led_31_grp_a";
512 };
513
514 pins_hs_uart: hs_uart-pins {
515 function = "hs_uart";
516 groups = "hs_uart_grp";
517 };
518
519 pins_i2c_a: i2c-a-pins {
520 function = "i2c";
521 groups = "i2c_grp_a";
522 };
523
524 pins_i2c_b: i2c-b-pins {
525 function = "i2c";
526 groups = "i2c_grp_b";
527 };
528
529 pins_i2s: i2s-pins {
530 function = "i2s";
531 groups = "i2s_grp";
532 };
533
534 pins_nand_ctrl: nand_ctrl-pins {
535 function = "nand_ctrl";
536 groups = "nand_ctrl_grp";
537 };
538
539 pins_nand_data: nand_data-pins {
540 function = "nand_data";
541 groups = "nand_data_grp";
542 };
543
544 pins_emmc_ctrl: emmc_ctrl-pins {
545 function = "emmc_ctrl";
546 groups = "emmc_ctrl_grp";
547 };
548
549 pins_usb0_pwr: usb0_pwr-pins {
550 function = "usb0_pwr";
551 groups = "usb0_pwr_grp";
552 };
553
554 pins_usb1_pwr: usb1_pwr-pins {
555 function = "usb1_pwr";
556 groups = "usb1_pwr_grp";
557 };
558 };
559
560 uart0: serial@640 {
561 compatible = "brcm,bcm6345-uart";
562 reg = <0x640 0x18>;
563 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&periph_clk>;
565 clock-names = "refclk";
566 status = "okay";
567 };
568
569 leds: leds@800 {
570 compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
571 reg = <0x800 0xdc>;
572
573 #address-cells = <1>;
574 #size-cells = <0>;
575 };
576
577 hsspi: spi@1000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
581 reg = <0x1000 0x600>;
582 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&hsspi_pll &hsspi_pll>;
584 clock-names = "hsspi", "pll";
585 num-cs = <8>;
586 status = "disabled";
587 };
588
589 nand_controller: nand-controller@1800 {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
593 reg = <0x1800 0x600>, <0x2000 0x10>;
594 reg-names = "nand", "nand-int-base";
595 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "nand_ctlrdy";
597 brcm,wp-not-connected;
598 status = "disabled";
599
600 nandcs: nand@0 {
601 compatible = "brcm,nandcs";
602 reg = <0>;
603 };
604 };
605
606 i2c@2100 {
607 compatible = "brcm,brcmper-i2c";
608 reg = <0x2100 0x58>;
609 clock-frequency = <97500>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pins_i2c_a>;
612 status = "disabled";
613 };
614
615 misc@2600 {
616 compatible = "brcm,misc", "simple-mfd";
617 reg = <0x2600 0xe4>;
618
619 #address-cells = <1>;
620 #size-cells = <1>;
621 ranges = <0x00 0x2600 0xe4>;
622
623 reset-controller@2644 {
624 compatible = "brcm,bcm4908-misc-pcie-reset";
625 reg = <0x44 0x04>;
626 #reset-cells = <1>;
627 };
628 };
629 };
630
631 reboot {
632 compatible = "syscon-reboot";
633 regmap = <&twd>;
634 offset = <0x34>;
635 mask = <1>;
636 };
637 };
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