1 /*
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /memreserve/ 0x81000000 0x00200000;
34
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
37
38 / {
39 compatible = "brcm,ns2";
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
43
44 cpus {
45 #address-cells = <2>;
46 #size-cells = <0>;
47
48 A57_0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a57";
51 reg = <0 0>;
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
54 };
55
56 A57_1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a57";
59 reg = <0 1>;
60 enable-method = "psci";
61 next-level-cache = <&CLUSTER0_L2>;
62 };
63
64 A57_2: cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a57";
67 reg = <0 2>;
68 enable-method = "psci";
69 next-level-cache = <&CLUSTER0_L2>;
70 };
71
72 A57_3: cpu@3 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a57";
75 reg = <0 3>;
76 enable-method = "psci";
77 next-level-cache = <&CLUSTER0_L2>;
78 };
79
80 CLUSTER0_L2: l2-cache@0 {
81 compatible = "cache";
82 cache-level = <2>;
83 cache-unified;
84 };
85 };
86
87 psci {
88 compatible = "arm,psci-1.0";
89 method = "smc";
90 };
91
92 timer {
93 compatible = "arm,armv8-timer";
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
95 IRQ_TYPE_LEVEL_LOW)>,
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
97 IRQ_TYPE_LEVEL_LOW)>,
98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
99 IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
101 IRQ_TYPE_LEVEL_LOW)>;
102 };
103
104 pmu {
105 compatible = "arm,cortex-a57-pmu";
106 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-affinity = <&A57_0>,
111 <&A57_1>,
112 <&A57_2>,
113 <&A57_3>;
114 };
115
116 pcie0: pcie@20020000 {
117 compatible = "brcm,iproc-pcie";
118 reg = <0 0x20020000 0 0x1000>;
119 dma-coherent;
120
121 #interrupt-cells = <1>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
124
125 linux,pci-domain = <0>;
126
127 bus-range = <0x00 0xff>;
128
129 #address-cells = <3>;
130 #size-cells = <2>;
131 device_type = "pci";
132 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
133
134 brcm,pcie-ob;
135 brcm,pcie-ob-oarr-size;
136 brcm,pcie-ob-axi-offset = <0x00000000>;
137 brcm,pcie-ob-window-size = <256>;
138
139 status = "disabled";
140
141 phys = <&pci_phy0>;
142 phy-names = "pcie-phy";
143
144 msi-parent = <&v2m0>;
145 };
146
147 pcie4: pcie@50020000 {
148 compatible = "brcm,iproc-pcie";
149 reg = <0 0x50020000 0 0x1000>;
150 dma-coherent;
151
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
155
156 linux,pci-domain = <4>;
157
158 bus-range = <0x00 0xff>;
159
160 #address-cells = <3>;
161 #size-cells = <2>;
162 device_type = "pci";
163 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
164
165 brcm,pcie-ob;
166 brcm,pcie-ob-oarr-size;
167 brcm,pcie-ob-axi-offset = <0x30000000>;
168 brcm,pcie-ob-window-size = <256>;
169
170 status = "disabled";
171
172 phys = <&pci_phy1>;
173 phy-names = "pcie-phy";
174
175 msi-parent = <&v2m0>;
176 };
177
178 pcie8: pcie@60c00000 {
179 compatible = "brcm,iproc-pcie-paxc";
180 reg = <0 0x60c00000 0 0x1000>;
181 dma-coherent;
182 linux,pci-domain = <8>;
183
184 bus-range = <0x0 0x1>;
185
186 #address-cells = <3>;
187 #size-cells = <2>;
188 device_type = "pci";
189 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
190
191 status = "disabled";
192
193 msi-parent = <&v2m0>;
194 };
195
196 soc: soc {
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0 0 0 0xffffffff>;
201
202 #include "ns2-clock.dtsi"
203
204 enet: ethernet@61000000 {
205 compatible = "brcm,ns2-amac";
206 reg = <0x61000000 0x1000>,
207 <0x61090000 0x1000>,
208 <0x61030000 0x100>;
209 reg-names = "amac_base", "idm_base", "nicpm_base";
210 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
211 dma-coherent;
212 phy-handle = <&gphy0>;
213 phy-mode = "rgmii";
214 status = "disabled";
215 };
216
217 pdc0: iproc-pdc0@612c0000 {
218 compatible = "brcm,iproc-pdc-mbox";
219 reg = <0x612c0000 0x445>; /* PDC FS0 regs */
220 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
221 #mbox-cells = <1>;
222 dma-coherent;
223 brcm,rx-status-len = <32>;
224 brcm,use-bcm-hdr;
225 };
226
227 crypto0: crypto@612d0000 {
228 compatible = "brcm,spum-crypto";
229 reg = <0x612d0000 0x900>;
230 mboxes = <&pdc0 0>;
231 };
232
233 pdc1: iproc-pdc1@612e0000 {
234 compatible = "brcm,iproc-pdc-mbox";
235 reg = <0x612e0000 0x445>; /* PDC FS1 regs */
236 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
237 #mbox-cells = <1>;
238 dma-coherent;
239 brcm,rx-status-len = <32>;
240 brcm,use-bcm-hdr;
241 };
242
243 crypto1: crypto@612f0000 {
244 compatible = "brcm,spum-crypto";
245 reg = <0x612f0000 0x900>;
246 mboxes = <&pdc1 0>;
247 };
248
249 pdc2: iproc-pdc2@61300000 {
250 compatible = "brcm,iproc-pdc-mbox";
251 reg = <0x61300000 0x445>; /* PDC FS2 regs */
252 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
253 #mbox-cells = <1>;
254 dma-coherent;
255 brcm,rx-status-len = <32>;
256 brcm,use-bcm-hdr;
257 };
258
259 crypto2: crypto@61310000 {
260 compatible = "brcm,spum-crypto";
261 reg = <0x61310000 0x900>;
262 mboxes = <&pdc2 0>;
263 };
264
265 pdc3: iproc-pdc3@61320000 {
266 compatible = "brcm,iproc-pdc-mbox";
267 reg = <0x61320000 0x445>; /* PDC FS3 regs */
268 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
269 #mbox-cells = <1>;
270 dma-coherent;
271 brcm,rx-status-len = <32>;
272 brcm,use-bcm-hdr;
273 };
274
275 crypto3: crypto@61330000 {
276 compatible = "brcm,spum-crypto";
277 reg = <0x61330000 0x900>;
278 mboxes = <&pdc3 0>;
279 };
280
281 dma0: dma-controller@61360000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x61360000 0x1000>;
284 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
293 #dma-cells = <1>;
294 clocks = <&iprocslow>;
295 clock-names = "apb_pclk";
296 };
297
298 smmu: iommu@64000000 {
299 compatible = "arm,mmu-500";
300 reg = <0x64000000 0x40000>;
301 #global-interrupts = <2>;
302 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
336 #iommu-cells = <1>;
337 };
338
339 pinctrl: pinctrl@6501d130 {
340 compatible = "brcm,ns2-pinmux";
341 reg = <0x6501d130 0x08>,
342 <0x660a0028 0x04>,
343 <0x660009b0 0x40>;
344 };
345
346 gpio_aon: gpio@65024800 {
347 compatible = "brcm,iproc-gpio";
348 reg = <0x65024800 0x50>,
349 <0x65024008 0x18>;
350 ngpios = <6>;
351 #gpio-cells = <2>;
352 gpio-controller;
353 };
354
355 gic: interrupt-controller@65210000 {
356 compatible = "arm,gic-400";
357 #interrupt-cells = <3>;
358 interrupt-controller;
359 reg = <0x65210000 0x1000>,
360 <0x65220000 0x1000>,
361 <0x65240000 0x2000>,
362 <0x65260000 0x1000>;
363 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
364 IRQ_TYPE_LEVEL_HIGH)>;
365
366 #address-cells = <1>;
367 #size-cells = <1>;
368 ranges = <0 0x652e0000 0x80000>;
369
370 v2m0: v2m@0 {
371 compatible = "arm,gic-v2m-frame";
372 interrupt-parent = <&gic>;
373 msi-controller;
374 reg = <0x00000 0x1000>;
375 arm,msi-base-spi = <72>;
376 arm,msi-num-spis = <16>;
377 };
378
379 v2m1: v2m@10000 {
380 compatible = "arm,gic-v2m-frame";
381 interrupt-parent = <&gic>;
382 msi-controller;
383 reg = <0x10000 0x1000>;
384 arm,msi-base-spi = <88>;
385 arm,msi-num-spis = <16>;
386 };
387
388 v2m2: v2m@20000 {
389 compatible = "arm,gic-v2m-frame";
390 interrupt-parent = <&gic>;
391 msi-controller;
392 reg = <0x20000 0x1000>;
393 arm,msi-base-spi = <104>;
394 arm,msi-num-spis = <16>;
395 };
396
397 v2m3: v2m@30000 {
398 compatible = "arm,gic-v2m-frame";
399 interrupt-parent = <&gic>;
400 msi-controller;
401 reg = <0x30000 0x1000>;
402 arm,msi-base-spi = <120>;
403 arm,msi-num-spis = <16>;
404 };
405
406 v2m4: v2m@40000 {
407 compatible = "arm,gic-v2m-frame";
408 interrupt-parent = <&gic>;
409 msi-controller;
410 reg = <0x40000 0x1000>;
411 arm,msi-base-spi = <136>;
412 arm,msi-num-spis = <16>;
413 };
414
415 v2m5: v2m@50000 {
416 compatible = "arm,gic-v2m-frame";
417 interrupt-parent = <&gic>;
418 msi-controller;
419 reg = <0x50000 0x1000>;
420 arm,msi-base-spi = <152>;
421 arm,msi-num-spis = <16>;
422 };
423
424 v2m6: v2m@60000 {
425 compatible = "arm,gic-v2m-frame";
426 interrupt-parent = <&gic>;
427 msi-controller;
428 reg = <0x60000 0x1000>;
429 arm,msi-base-spi = <168>;
430 arm,msi-num-spis = <16>;
431 };
432
433 v2m7: v2m@70000 {
434 compatible = "arm,gic-v2m-frame";
435 interrupt-parent = <&gic>;
436 msi-controller;
437 reg = <0x70000 0x1000>;
438 arm,msi-base-spi = <184>;
439 arm,msi-num-spis = <16>;
440 };
441 };
442
443 cci@65590000 {
444 compatible = "arm,cci-400";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 reg = <0x65590000 0x1000>;
448 ranges = <0 0x65590000 0x10000>;
449
450 pmu@9000 {
451 compatible = "arm,cci-400-pmu,r1",
452 "arm,cci-400-pmu";
453 reg = <0x9000 0x4000>;
454 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
460 };
461 };
462
463 usbdrd_phy: phy@66000960 {
464 #phy-cells = <0>;
465 compatible = "brcm,ns2-drd-phy";
466 reg = <0x66000960 0x24>,
467 <0x67012800 0x4>,
468 <0x6501d148 0x4>,
469 <0x664d0700 0x4>;
470 reg-names = "icfg", "rst-ctrl",
471 "crmu-ctrl", "usb2-strap";
472 id-gpios = <&gpio_g 30 0>;
473 vbus-gpios = <&gpio_g 31 0>;
474 status = "disabled";
475 };
476
477 pwm: pwm@66010000 {
478 compatible = "brcm,iproc-pwm";
479 reg = <0x66010000 0x28>;
480 clocks = <&osc>;
481 #pwm-cells = <3>;
482 status = "disabled";
483 };
484
485 mdio_mux_iproc: mdio-mux@66020000 {
486 compatible = "brcm,mdio-mux-iproc";
487 reg = <0x66020000 0x250>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 mdio@0 {
492 reg = <0x0>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495
496 pci_phy0: pci-phy@0 {
497 compatible = "brcm,ns2-pcie-phy";
498 reg = <0x0>;
499 #phy-cells = <0>;
500 status = "disabled";
501 };
502 };
503
504 mdio@7 {
505 reg = <0x7>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508
509 pci_phy1: pci-phy@0 {
510 compatible = "brcm,ns2-pcie-phy";
511 reg = <0x0>;
512 #phy-cells = <0>;
513 status = "disabled";
514 };
515 };
516
517 mdio@10 {
518 reg = <0x10>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 };
522 };
523
524 timer0: timer@66030000 {
525 compatible = "arm,sp804", "arm,primecell";
526 reg = <0x66030000 0x1000>;
527 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&iprocslow>,
529 <&iprocslow>,
530 <&iprocslow>;
531 clock-names = "timer1", "timer2", "apb_pclk";
532 };
533
534 timer1: timer@66040000 {
535 compatible = "arm,sp804", "arm,primecell";
536 reg = <0x66040000 0x1000>;
537 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&iprocslow>,
539 <&iprocslow>,
540 <&iprocslow>;
541 clock-names = "timer1", "timer2", "apb_pclk";
542 };
543
544 timer2: timer@66050000 {
545 compatible = "arm,sp804", "arm,primecell";
546 reg = <0x66050000 0x1000>;
547 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&iprocslow>,
549 <&iprocslow>,
550 <&iprocslow>;
551 clock-names = "timer1", "timer2", "apb_pclk";
552 };
553
554 timer3: timer@66060000 {
555 compatible = "arm,sp804", "arm,primecell";
556 reg = <0x66060000 0x1000>;
557 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&iprocslow>,
559 <&iprocslow>,
560 <&iprocslow>;
561 clock-names = "timer1", "timer2", "apb_pclk";
562 };
563
564 i2c0: i2c@66080000 {
565 compatible = "brcm,iproc-i2c";
566 reg = <0x66080000 0x100>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
570 clock-frequency = <100000>;
571 status = "disabled";
572 };
573
574 wdt0: watchdog@66090000 {
575 compatible = "arm,sp805", "arm,primecell";
576 reg = <0x66090000 0x1000>;
577 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&iprocslow>, <&iprocslow>;
579 clock-names = "wdog_clk", "apb_pclk";
580 };
581
582 gpio_g: gpio@660a0000 {
583 compatible = "brcm,iproc-gpio";
584 reg = <0x660a0000 0x50>;
585 ngpios = <32>;
586 #gpio-cells = <2>;
587 gpio-controller;
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
591 };
592
593 i2c1: i2c@660b0000 {
594 compatible = "brcm,iproc-i2c";
595 reg = <0x660b0000 0x100>;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
599 clock-frequency = <100000>;
600 status = "disabled";
601 };
602
603 uart0: serial@66100000 {
604 compatible = "snps,dw-apb-uart";
605 reg = <0x66100000 0x100>;
606 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&iprocslow>;
608 reg-shift = <2>;
609 reg-io-width = <4>;
610 status = "disabled";
611 };
612
613 uart1: serial@66110000 {
614 compatible = "snps,dw-apb-uart";
615 reg = <0x66110000 0x100>;
616 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&iprocslow>;
618 reg-shift = <2>;
619 reg-io-width = <4>;
620 status = "disabled";
621 };
622
623 uart2: serial@66120000 {
624 compatible = "snps,dw-apb-uart";
625 reg = <0x66120000 0x100>;
626 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&iprocslow>;
628 reg-shift = <2>;
629 reg-io-width = <4>;
630 status = "disabled";
631 };
632
633 uart3: serial@66130000 {
634 compatible = "snps,dw-apb-uart";
635 reg = <0x66130000 0x100>;
636 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
637 reg-shift = <2>;
638 reg-io-width = <4>;
639 clocks = <&osc>;
640 status = "disabled";
641 };
642
643 ssp0: spi@66180000 {
644 compatible = "arm,pl022", "arm,primecell";
645 reg = <0x66180000 0x1000>;
646 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&iprocslow>, <&iprocslow>;
648 clock-names = "sspclk", "apb_pclk";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 status = "disabled";
652 };
653
654 ssp1: spi@66190000 {
655 compatible = "arm,pl022", "arm,primecell";
656 reg = <0x66190000 0x1000>;
657 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&iprocslow>, <&iprocslow>;
659 clock-names = "sspclk", "apb_pclk";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 status = "disabled";
663 };
664
665 hwrng: hwrng@66220000 {
666 compatible = "brcm,iproc-rng200";
667 reg = <0x66220000 0x28>;
668 };
669
670 sata_phy: sata_phy@663f0100 {
671 compatible = "brcm,iproc-ns2-sata-phy";
672 reg = <0x663f0100 0x1f00>,
673 <0x663f004c 0x10>;
674 reg-names = "phy", "phy-ctrl";
675 #address-cells = <1>;
676 #size-cells = <0>;
677
678 sata_phy0: sata-phy@0 {
679 reg = <0>;
680 #phy-cells = <0>;
681 status = "disabled";
682 };
683
684 sata_phy1: sata-phy@1 {
685 reg = <1>;
686 #phy-cells = <0>;
687 status = "disabled";
688 };
689 };
690
691 sata: sata@663f2000 {
692 compatible = "brcm,iproc-ahci", "generic-ahci";
693 reg = <0x663f2000 0x1000>;
694 dma-coherent;
695 reg-names = "ahci";
696 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
697 #address-cells = <1>;
698 #size-cells = <0>;
699 status = "disabled";
700
701 sata0: sata-port@0 {
702 reg = <0>;
703 phys = <&sata_phy0>;
704 phy-names = "sata-phy";
705 };
706
707 sata1: sata-port@1 {
708 reg = <1>;
709 phys = <&sata_phy1>;
710 phy-names = "sata-phy";
711 };
712 };
713
714 sdio0: sdhci@66420000 {
715 compatible = "brcm,sdhci-iproc-cygnus";
716 reg = <0x66420000 0x100>;
717 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
718 dma-coherent;
719 bus-width = <8>;
720 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
721 status = "disabled";
722 };
723
724 sdio1: sdhci@66430000 {
725 compatible = "brcm,sdhci-iproc-cygnus";
726 reg = <0x66430000 0x100>;
727 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
728 dma-coherent;
729 bus-width = <8>;
730 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
731 status = "disabled";
732 };
733
734 nand: nand@66460000 {
735 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
736 reg = <0x66460000 0x600>,
737 <0x67015408 0x600>,
738 <0x66460f00 0x20>;
739 reg-names = "nand", "iproc-idm", "iproc-ext";
740 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
741
742 #address-cells = <1>;
743 #size-cells = <0>;
744
745 brcm,nand-has-wp;
746 };
747
748 qspi: spi@66470200 {
749 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
750 reg = <0x66470200 0x184>,
751 <0x66470000 0x124>,
752 <0x67017408 0x004>,
753 <0x664703a0 0x01c>;
754 reg-names = "mspi", "bspi", "intr_regs",
755 "intr_status_reg";
756 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "spi_l1_intr";
758 clocks = <&iprocmed>;
759 clock-names = "iprocmed";
760 num-cs = <2>;
761 #address-cells = <1>;
762 #size-cells = <0>;
763 };
764
765 };
766 };
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