1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung Exynos7 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 */
8
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
12 / {
13 compatible = "samsung,exynos7";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 pinctrl0 = &pinctrl_alive;
20 pinctrl1 = &pinctrl_bus0;
21 pinctrl2 = &pinctrl_nfc;
22 pinctrl3 = &pinctrl_touch;
23 pinctrl4 = &pinctrl_ff;
24 pinctrl5 = &pinctrl_ese;
25 pinctrl6 = &pinctrl_fsys0;
26 pinctrl7 = &pinctrl_fsys1;
27 pinctrl8 = &pinctrl_bus1;
28 };
29
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
32 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
36 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
37 <&cpu_atlas2>, <&cpu_atlas3>;
38 };
39
40 fin_pll: clock {
41 /* XXTI */
42 compatible = "fixed-clock";
43 clock-output-names = "fin_pll";
44 #clock-cells = <0>;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu_atlas0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a57";
54 reg = <0x0>;
55 enable-method = "psci";
56 i-cache-size = <0xc000>;
57 i-cache-line-size = <64>;
58 i-cache-sets = <256>;
59 d-cache-size = <0x8000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <256>;
62 next-level-cache = <&atlas_l2>;
63 };
64
65 cpu_atlas1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a57";
68 reg = <0x1>;
69 enable-method = "psci";
70 i-cache-size = <0xc000>;
71 i-cache-line-size = <64>;
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <256>;
76 next-level-cache = <&atlas_l2>;
77 };
78
79 cpu_atlas2: cpu@2 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a57";
82 reg = <0x2>;
83 enable-method = "psci";
84 i-cache-size = <0xc000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <256>;
90 next-level-cache = <&atlas_l2>;
91 };
92
93 cpu_atlas3: cpu@3 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a57";
96 reg = <0x3>;
97 enable-method = "psci";
98 i-cache-size = <0xc000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <256>;
104 next-level-cache = <&atlas_l2>;
105 };
106
107 atlas_l2: l2-cache0 {
108 compatible = "cache";
109 cache-level = <2>;
110 cache-unified;
111 cache-size = <0x200000>;
112 cache-line-size = <64>;
113 cache-sets = <2048>;
114 };
115 };
116
117 psci {
118 compatible = "arm,psci";
119 method = "smc";
120 cpu_off = <0x84000002>;
121 cpu_on = <0xc4000003>;
122 };
123
124 soc: soc@0 {
125 compatible = "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges = <0 0 0 0x18000000>;
129
130 chipid@10000000 {
131 compatible = "samsung,exynos7-chipid",
132 "samsung,exynos4210-chipid";
133 reg = <0x10000000 0x100>;
134 };
135
136 gic: interrupt-controller@11001000 {
137 compatible = "arm,gic-400";
138 #interrupt-cells = <3>;
139 #address-cells = <0>;
140 interrupt-controller;
141 reg = <0x11001000 0x1000>,
142 <0x11002000 0x2000>,
143 <0x11004000 0x2000>,
144 <0x11006000 0x2000>;
145 };
146
147 pdma0: dma-controller@10e10000 {
148 compatible = "arm,pl330", "arm,primecell";
149 reg = <0x10e10000 0x1000>;
150 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&clock_fsys0 ACLK_PDMA0>;
152 clock-names = "apb_pclk";
153 #dma-cells = <1>;
154 };
155
156 pdma1: dma-controller@10eb0000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0x10eb0000 0x1000>;
159 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clock_fsys0 ACLK_PDMA1>;
161 clock-names = "apb_pclk";
162 #dma-cells = <1>;
163 };
164
165 clock_topc: clock-controller@10570000 {
166 compatible = "samsung,exynos7-clock-topc";
167 reg = <0x10570000 0x10000>;
168 #clock-cells = <1>;
169 };
170
171 clock_top0: clock-controller@105d0000 {
172 compatible = "samsung,exynos7-clock-top0";
173 reg = <0x105d0000 0xb000>;
174 #clock-cells = <1>;
175 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
176 <&clock_topc DOUT_SCLK_BUS1_PLL>,
177 <&clock_topc DOUT_SCLK_CC_PLL>,
178 <&clock_topc DOUT_SCLK_MFC_PLL>,
179 <&clock_topc DOUT_SCLK_AUD_PLL>;
180 clock-names = "fin_pll", "dout_sclk_bus0_pll",
181 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
182 "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
183 };
184
185 clock_top1: clock-controller@105e0000 {
186 compatible = "samsung,exynos7-clock-top1";
187 reg = <0x105e0000 0xb000>;
188 #clock-cells = <1>;
189 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
190 <&clock_topc DOUT_SCLK_BUS1_PLL>,
191 <&clock_topc DOUT_SCLK_CC_PLL>,
192 <&clock_topc DOUT_SCLK_MFC_PLL>;
193 clock-names = "fin_pll", "dout_sclk_bus0_pll",
194 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
195 "dout_sclk_mfc_pll";
196 };
197
198 clock_ccore: clock-controller@105b0000 {
199 compatible = "samsung,exynos7-clock-ccore";
200 reg = <0x105b0000 0xd00>;
201 #clock-cells = <1>;
202 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
203 clock-names = "fin_pll", "dout_aclk_ccore_133";
204 };
205
206 clock_peric0: clock-controller@13610000 {
207 compatible = "samsung,exynos7-clock-peric0";
208 reg = <0x13610000 0xd00>;
209 #clock-cells = <1>;
210 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
211 <&clock_top0 CLK_SCLK_UART0>;
212 clock-names = "fin_pll", "dout_aclk_peric0_66",
213 "sclk_uart0";
214 };
215
216 clock_peric1: clock-controller@14c80000 {
217 compatible = "samsung,exynos7-clock-peric1";
218 reg = <0x14c80000 0xd00>;
219 #clock-cells = <1>;
220 clocks = <&fin_pll>,
221 <&clock_top0 DOUT_ACLK_PERIC1>,
222 <&clock_top0 CLK_SCLK_UART1>,
223 <&clock_top0 CLK_SCLK_UART2>,
224 <&clock_top0 CLK_SCLK_UART3>,
225 <&clock_top0 CLK_SCLK_SPI0>,
226 <&clock_top0 CLK_SCLK_SPI1>,
227 <&clock_top0 CLK_SCLK_SPI2>,
228 <&clock_top0 CLK_SCLK_SPI3>,
229 <&clock_top0 CLK_SCLK_SPI4>,
230 <&clock_top0 CLK_SCLK_I2S1>,
231 <&clock_top0 CLK_SCLK_PCM1>,
232 <&clock_top0 CLK_SCLK_SPDIF>;
233 clock-names = "fin_pll",
234 "dout_aclk_peric1_66",
235 "sclk_uart1",
236 "sclk_uart2",
237 "sclk_uart3",
238 "sclk_spi0",
239 "sclk_spi1",
240 "sclk_spi2",
241 "sclk_spi3",
242 "sclk_spi4",
243 "sclk_i2s1",
244 "sclk_pcm1",
245 "sclk_spdif";
246 };
247
248 clock_peris: clock-controller@10040000 {
249 compatible = "samsung,exynos7-clock-peris";
250 reg = <0x10040000 0xd00>;
251 #clock-cells = <1>;
252 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
253 clock-names = "fin_pll", "dout_aclk_peris_66";
254 };
255
256 clock_fsys0: clock-controller@10e90000 {
257 compatible = "samsung,exynos7-clock-fsys0";
258 reg = <0x10e90000 0xd00>;
259 #clock-cells = <1>;
260 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
261 <&clock_top1 DOUT_SCLK_MMC2>;
262 clock-names = "fin_pll", "dout_aclk_fsys0_200",
263 "dout_sclk_mmc2";
264 };
265
266 clock_fsys1: clock-controller@156e0000 {
267 compatible = "samsung,exynos7-clock-fsys1";
268 reg = <0x156e0000 0xd00>;
269 #clock-cells = <1>;
270 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
271 <&clock_top1 DOUT_SCLK_MMC0>,
272 <&clock_top1 DOUT_SCLK_MMC1>,
273 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
274 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
275 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
276 clock-names = "fin_pll", "dout_aclk_fsys1_200",
277 "dout_sclk_mmc0", "dout_sclk_mmc1",
278 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
279 "dout_sclk_phy_fsys1_26m";
280 };
281
282 serial_0: serial@13630000 {
283 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
284 reg = <0x13630000 0x100>;
285 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clock_peric0 PCLK_UART0>,
287 <&clock_peric0 SCLK_UART0>;
288 clock-names = "uart", "clk_uart_baud0";
289 status = "disabled";
290 };
291
292 serial_1: serial@14c20000 {
293 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
294 reg = <0x14c20000 0x100>;
295 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clock_peric1 PCLK_UART1>,
297 <&clock_peric1 SCLK_UART1>;
298 clock-names = "uart", "clk_uart_baud0";
299 status = "disabled";
300 };
301
302 serial_2: serial@14c30000 {
303 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
304 reg = <0x14c30000 0x100>;
305 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clock_peric1 PCLK_UART2>,
307 <&clock_peric1 SCLK_UART2>;
308 clock-names = "uart", "clk_uart_baud0";
309 status = "disabled";
310 };
311
312 serial_3: serial@14c40000 {
313 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
314 reg = <0x14c40000 0x100>;
315 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clock_peric1 PCLK_UART3>,
317 <&clock_peric1 SCLK_UART3>;
318 clock-names = "uart", "clk_uart_baud0";
319 status = "disabled";
320 };
321
322 pinctrl_alive: pinctrl@10580000 {
323 compatible = "samsung,exynos7-pinctrl";
324 reg = <0x10580000 0x1000>;
325
326 wakeup-interrupt-controller {
327 compatible = "samsung,exynos7-wakeup-eint";
328 interrupt-parent = <&gic>;
329 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
330 };
331 };
332
333 pinctrl_bus0: pinctrl@13470000 {
334 compatible = "samsung,exynos7-pinctrl";
335 reg = <0x13470000 0x1000>;
336 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
337 };
338
339 pinctrl_nfc: pinctrl@14cd0000 {
340 compatible = "samsung,exynos7-pinctrl";
341 reg = <0x14cd0000 0x1000>;
342 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
343 };
344
345 pinctrl_touch: pinctrl@14ce0000 {
346 compatible = "samsung,exynos7-pinctrl";
347 reg = <0x14ce0000 0x1000>;
348 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
349 };
350
351 pinctrl_ff: pinctrl@14c90000 {
352 compatible = "samsung,exynos7-pinctrl";
353 reg = <0x14c90000 0x1000>;
354 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
355 };
356
357 pinctrl_ese: pinctrl@14ca0000 {
358 compatible = "samsung,exynos7-pinctrl";
359 reg = <0x14ca0000 0x1000>;
360 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
361 };
362
363 pinctrl_fsys0: pinctrl@10e60000 {
364 compatible = "samsung,exynos7-pinctrl";
365 reg = <0x10e60000 0x1000>;
366 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
367 };
368
369 pinctrl_fsys1: pinctrl@15690000 {
370 compatible = "samsung,exynos7-pinctrl";
371 reg = <0x15690000 0x1000>;
372 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
373 };
374
375 pinctrl_bus1: pinctrl@14870000 {
376 compatible = "samsung,exynos7-pinctrl";
377 reg = <0x14870000 0x1000>;
378 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
379 };
380
381 hsi2c_0: i2c@13640000 {
382 compatible = "samsung,exynos7-hsi2c";
383 reg = <0x13640000 0x1000>;
384 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&hs_i2c0_bus>;
389 clocks = <&clock_peric0 PCLK_HSI2C0>;
390 clock-names = "hsi2c";
391 status = "disabled";
392 };
393
394 hsi2c_1: i2c@13650000 {
395 compatible = "samsung,exynos7-hsi2c";
396 reg = <0x13650000 0x1000>;
397 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&hs_i2c1_bus>;
402 clocks = <&clock_peric0 PCLK_HSI2C1>;
403 clock-names = "hsi2c";
404 status = "disabled";
405 };
406
407 hsi2c_2: i2c@14e60000 {
408 compatible = "samsung,exynos7-hsi2c";
409 reg = <0x14e60000 0x1000>;
410 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&hs_i2c2_bus>;
415 clocks = <&clock_peric1 PCLK_HSI2C2>;
416 clock-names = "hsi2c";
417 status = "disabled";
418 };
419
420 hsi2c_3: i2c@14e70000 {
421 compatible = "samsung,exynos7-hsi2c";
422 reg = <0x14e70000 0x1000>;
423 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
425 #size-cells = <0>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&hs_i2c3_bus>;
428 clocks = <&clock_peric1 PCLK_HSI2C3>;
429 clock-names = "hsi2c";
430 status = "disabled";
431 };
432
433 hsi2c_4: i2c@13660000 {
434 compatible = "samsung,exynos7-hsi2c";
435 reg = <0x13660000 0x1000>;
436 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&hs_i2c4_bus>;
441 clocks = <&clock_peric0 PCLK_HSI2C4>;
442 clock-names = "hsi2c";
443 status = "disabled";
444 };
445
446 hsi2c_5: i2c@13670000 {
447 compatible = "samsung,exynos7-hsi2c";
448 reg = <0x13670000 0x1000>;
449 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&hs_i2c5_bus>;
454 clocks = <&clock_peric0 PCLK_HSI2C5>;
455 clock-names = "hsi2c";
456 status = "disabled";
457 };
458
459 hsi2c_6: i2c@14e00000 {
460 compatible = "samsung,exynos7-hsi2c";
461 reg = <0x14e00000 0x1000>;
462 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&hs_i2c6_bus>;
467 clocks = <&clock_peric1 PCLK_HSI2C6>;
468 clock-names = "hsi2c";
469 status = "disabled";
470 };
471
472 hsi2c_7: i2c@13e10000 {
473 compatible = "samsung,exynos7-hsi2c";
474 reg = <0x13e10000 0x1000>;
475 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&hs_i2c7_bus>;
480 clocks = <&clock_peric1 PCLK_HSI2C7>;
481 clock-names = "hsi2c";
482 status = "disabled";
483 };
484
485 hsi2c_8: i2c@14e20000 {
486 compatible = "samsung,exynos7-hsi2c";
487 reg = <0x14e20000 0x1000>;
488 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&hs_i2c8_bus>;
493 clocks = <&clock_peric1 PCLK_HSI2C8>;
494 clock-names = "hsi2c";
495 status = "disabled";
496 };
497
498 hsi2c_9: i2c@13680000 {
499 compatible = "samsung,exynos7-hsi2c";
500 reg = <0x13680000 0x1000>;
501 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&hs_i2c9_bus>;
506 clocks = <&clock_peric0 PCLK_HSI2C9>;
507 clock-names = "hsi2c";
508 status = "disabled";
509 };
510
511 hsi2c_10: i2c@13690000 {
512 compatible = "samsung,exynos7-hsi2c";
513 reg = <0x13690000 0x1000>;
514 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&hs_i2c10_bus>;
519 clocks = <&clock_peric0 PCLK_HSI2C10>;
520 clock-names = "hsi2c";
521 status = "disabled";
522 };
523
524 hsi2c_11: i2c@136a0000 {
525 compatible = "samsung,exynos7-hsi2c";
526 reg = <0x136a0000 0x1000>;
527 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&hs_i2c11_bus>;
532 clocks = <&clock_peric0 PCLK_HSI2C11>;
533 clock-names = "hsi2c";
534 status = "disabled";
535 };
536
537 pmu_system_controller: system-controller@105c0000 {
538 compatible = "samsung,exynos7-pmu", "syscon";
539 reg = <0x105c0000 0x5000>;
540 };
541
542 rtc: rtc@10590000 {
543 compatible = "samsung,exynos7-rtc", "samsung,s3c6410-rtc";
544 reg = <0x10590000 0x100>;
545 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clock_ccore PCLK_RTC>;
548 clock-names = "rtc";
549 status = "disabled";
550 };
551
552 watchdog: watchdog@101d0000 {
553 compatible = "samsung,exynos7-wdt";
554 reg = <0x101d0000 0x100>;
555 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clock_peris PCLK_WDT>;
557 clock-names = "watchdog";
558 samsung,syscon-phandle = <&pmu_system_controller>;
559 status = "disabled";
560 };
561
562 gpu: gpu@14ac0000 {
563 compatible = "samsung,exynos7-mali",
564 "samsung,exynos5433-mali", "arm,mali-t760";
565 reg = <0x14ac0000 0x5000>;
566 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "job", "mmu", "gpu";
570 status = "disabled";
571 /* TODO: operating points for DVFS, cooling device */
572 };
573
574 mmc_0: mmc@15740000 {
575 compatible = "samsung,exynos7-dw-mshc-smu";
576 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <0x15740000 0x2000>;
580 clocks = <&clock_fsys1 ACLK_MMC0>,
581 <&clock_top1 CLK_SCLK_MMC0>;
582 clock-names = "biu", "ciu";
583 fifo-depth = <0x40>;
584 status = "disabled";
585 };
586
587 mmc_1: mmc@15750000 {
588 compatible = "samsung,exynos7-dw-mshc";
589 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x15750000 0x2000>;
593 clocks = <&clock_fsys1 ACLK_MMC1>,
594 <&clock_top1 CLK_SCLK_MMC1>;
595 clock-names = "biu", "ciu";
596 fifo-depth = <0x40>;
597 status = "disabled";
598 };
599
600 mmc_2: mmc@15560000 {
601 compatible = "samsung,exynos7-dw-mshc-smu";
602 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 reg = <0x15560000 0x2000>;
606 clocks = <&clock_fsys0 ACLK_MMC2>,
607 <&clock_top1 CLK_SCLK_MMC2>;
608 clock-names = "biu", "ciu";
609 fifo-depth = <0x40>;
610 status = "disabled";
611 };
612
613 adc: adc@13620000 {
614 compatible = "samsung,exynos7-adc";
615 reg = <0x13620000 0x100>;
616 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clock_peric0 PCLK_ADCIF>;
618 clock-names = "adc";
619 #io-channel-cells = <1>;
620 status = "disabled";
621 };
622
623 pwm: pwm@136c0000 {
624 compatible = "samsung,exynos7-pwm", "samsung,exynos4210-pwm";
625 reg = <0x136c0000 0x100>;
626 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
631 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
632 #pwm-cells = <3>;
633 clocks = <&clock_peric0 PCLK_PWM>;
634 clock-names = "timers";
635 };
636
637 tmuctrl_0: tmu@10060000 {
638 compatible = "samsung,exynos7-tmu";
639 reg = <0x10060000 0x200>;
640 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clock_peris PCLK_TMU>,
642 <&clock_peris SCLK_TMU>;
643 clock-names = "tmu_apbif", "tmu_sclk";
644 #thermal-sensor-cells = <0>;
645 };
646
647 ufs: ufs@15570000 {
648 compatible = "samsung,exynos7-ufs";
649 reg = <0x15570000 0x100>, /* 0: HCI standard */
650 <0x15570100 0x100>, /* 1: Vendor specificed */
651 <0x15571000 0x200>, /* 2: UNIPRO */
652 <0x15572000 0x300>; /* 3: UFS protector */
653 reg-names = "hci", "vs_hci", "unipro", "ufsp";
654 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
656 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
657 clock-names = "core_clk", "sclk_unipro_main";
658 freq-table-hz = <0 0>, <0 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
661 phys = <&ufs_phy>;
662 phy-names = "ufs-phy";
663 status = "disabled";
664 };
665
666 ufs_phy: ufs-phy@15571800 {
667 compatible = "samsung,exynos7-ufs-phy";
668 reg = <0x15571800 0x240>;
669 reg-names = "phy-pma";
670 samsung,pmu-syscon = <&pmu_system_controller>;
671 #phy-cells = <0>;
672 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
673 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
674 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
675 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
676 clock-names = "ref_clk", "rx1_symbol_clk",
677 "rx0_symbol_clk",
678 "tx0_symbol_clk";
679 };
680
681 usbdrd_phy: phy@15500000 {
682 compatible = "samsung,exynos7-usbdrd-phy";
683 reg = <0x15500000 0x100>;
684 clocks = <&clock_fsys0 ACLK_USBDRD300>,
685 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
686 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
687 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
688 <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
689 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
690 samsung,pmu-syscon = <&pmu_system_controller>;
691 #phy-cells = <1>;
692 };
693
694 usbdrd: usb@15400000 {
695 compatible = "samsung,exynos7-dwusb3";
696 clocks = <&clock_fsys0 ACLK_USBDRD300>,
697 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
698 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
699 clock-names = "usbdrd30", "usbdrd30_susp_clk",
700 "usbdrd30_axius_clk";
701 #address-cells = <1>;
702 #size-cells = <1>;
703 ranges = <0x0 0x15400000 0x10000>;
704
705 usb@0 {
706 compatible = "snps,dwc3";
707 reg = <0x0 0x10000>;
708 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
709 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
710 phy-names = "usb2-phy", "usb3-phy";
711 };
712 };
713 };
714
715 thermal-zones {
716 atlas_thermal: cluster0-thermal {
717 polling-delay-passive = <0>; /* milliseconds */
718 polling-delay = <0>; /* milliseconds */
719 thermal-sensors = <&tmuctrl_0>;
720 #include "exynos7-trip-points.dtsi"
721 };
722 };
723
724 timer {
725 compatible = "arm,armv8-timer";
726 interrupts = <GIC_PPI 13
727 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
728 <GIC_PPI 14
729 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
730 <GIC_PPI 11
731 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
732 <GIC_PPI 10
733 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
734 };
735 };
736
737 #include "exynos7-pinctrl.dtsi"
738 #include "arm/samsung/exynos-syscon-restart.dtsi"
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