1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
7 *
8 */
9
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "fsl,ls1012a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 crypto = &crypto;
22 rtc1 = &ftm_alarm0;
23 rtic-a = &rtic_a;
24 rtic-b = &rtic_b;
25 rtic-c = &rtic_c;
26 rtic-d = &rtic_d;
27 sec-mon = &sec_mon;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53";
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 #cooling-cells = <2>;
40 cpu-idle-states = <&CPU_PH20>;
41 };
42 };
43
44 idle-states {
45 /*
46 * PSCI node is not added default, U-boot will add missing
47 * parts if it determines to use PSCI.
48 */
49 entry-method = "psci";
50
51 CPU_PH20: cpu-ph20 {
52 compatible = "arm,idle-state";
53 idle-state-name = "PH20";
54 arm,psci-suspend-param = <0x0>;
55 entry-latency-us = <1000>;
56 exit-latency-us = <1000>;
57 min-residency-us = <3000>;
58 };
59 };
60
61 sysclk: sysclk {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <125000000>;
65 clock-output-names = "sysclk";
66 };
67
68 coreclk: coreclk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <100000000>;
72 clock-output-names = "coreclk";
73 };
74
75 timer {
76 compatible = "arm,armv8-timer";
77 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
78 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
79 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
80 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
81 };
82
83 pmu {
84 compatible = "arm,cortex-a53-pmu";
85 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
86 };
87
88 gic: interrupt-controller@1400000 {
89 compatible = "arm,gic-400";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
95 <0x0 0x1406000 0 0x2000>; /* GICV */
96 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
97 };
98
99 reboot {
100 compatible = "syscon-reboot";
101 regmap = <&dcfg>;
102 offset = <0xb0>;
103 mask = <0x02>;
104 };
105
106 thermal-zones {
107 cpu_thermal: cpu-thermal {
108 polling-delay-passive = <1000>;
109 polling-delay = <5000>;
110 thermal-sensors = <&tmu 0>;
111
112 trips {
113 cpu_alert: cpu-alert {
114 temperature = <85000>;
115 hysteresis = <2000>;
116 type = "passive";
117 };
118
119 cpu_crit: cpu-crit {
120 temperature = <95000>;
121 hysteresis = <2000>;
122 type = "critical";
123 };
124 };
125
126 cooling-maps {
127 map0 {
128 trip = <&cpu_alert>;
129 cooling-device =
130 <&cpu0 THERMAL_NO_LIMIT
131 THERMAL_NO_LIMIT>;
132 };
133 };
134 };
135 };
136
137 soc {
138 compatible = "simple-bus";
139 #address-cells = <2>;
140 #size-cells = <2>;
141 ranges;
142
143 qspi: spi@1550000 {
144 compatible = "fsl,ls1021a-qspi";
145 #address-cells = <1>;
146 #size-cells = <0>;
147 reg = <0x0 0x1550000 0x0 0x10000>,
148 <0x0 0x40000000 0x0 0x10000000>;
149 reg-names = "QuadSPI", "QuadSPI-memory";
150 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
151 clock-names = "qspi_en", "qspi";
152 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
153 QORIQ_CLK_PLL_DIV(1)>,
154 <&clockgen QORIQ_CLK_PLATFORM_PLL
155 QORIQ_CLK_PLL_DIV(1)>;
156 status = "disabled";
157 };
158
159 esdhc0: mmc@1560000 {
160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
161 reg = <0x0 0x1560000 0x0 0x10000>;
162 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
164 QORIQ_CLK_PLL_DIV(1)>;
165 voltage-ranges = <1800 1800 3300 3300>;
166 sdhci,auto-cmd12;
167 bus-width = <4>;
168 status = "disabled";
169 };
170
171 scfg: scfg@1570000 {
172 compatible = "fsl,ls1012a-scfg", "syscon";
173 reg = <0x0 0x1570000 0x0 0x10000>;
174 big-endian;
175 };
176
177 esdhc1: mmc@1580000 {
178 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
179 reg = <0x0 0x1580000 0x0 0x10000>;
180 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
182 QORIQ_CLK_PLL_DIV(1)>;
183 voltage-ranges = <1800 1800 3300 3300>;
184 sdhci,auto-cmd12;
185 broken-cd;
186 bus-width = <4>;
187 status = "disabled";
188 };
189
190 crypto: crypto@1700000 {
191 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
192 "fsl,sec-v4.0";
193 fsl,sec-era = <8>;
194 #address-cells = <1>;
195 #size-cells = <1>;
196 ranges = <0x0 0x00 0x1700000 0x100000>;
197 reg = <0x00 0x1700000 0x0 0x100000>;
198 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
199 dma-coherent;
200
201 sec_jr0: jr@10000 {
202 compatible = "fsl,sec-v5.4-job-ring",
203 "fsl,sec-v5.0-job-ring",
204 "fsl,sec-v4.0-job-ring";
205 reg = <0x10000 0x10000>;
206 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
207 };
208
209 sec_jr1: jr@20000 {
210 compatible = "fsl,sec-v5.4-job-ring",
211 "fsl,sec-v5.0-job-ring",
212 "fsl,sec-v4.0-job-ring";
213 reg = <0x20000 0x10000>;
214 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
215 };
216
217 sec_jr2: jr@30000 {
218 compatible = "fsl,sec-v5.4-job-ring",
219 "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x30000 0x10000>;
222 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
223 };
224
225 sec_jr3: jr@40000 {
226 compatible = "fsl,sec-v5.4-job-ring",
227 "fsl,sec-v5.0-job-ring",
228 "fsl,sec-v4.0-job-ring";
229 reg = <0x40000 0x10000>;
230 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
231 };
232
233 rtic@60000 {
234 compatible = "fsl,sec-v5.4-rtic",
235 "fsl,sec-v5.0-rtic",
236 "fsl,sec-v4.0-rtic";
237 #address-cells = <1>;
238 #size-cells = <1>;
239 reg = <0x60000 0x100>, <0x60e00 0x18>;
240 ranges = <0x0 0x60100 0x500>;
241
242 rtic_a: rtic-a@0 {
243 compatible = "fsl,sec-v5.4-rtic-memory",
244 "fsl,sec-v5.0-rtic-memory",
245 "fsl,sec-v4.0-rtic-memory";
246 reg = <0x00 0x20>, <0x100 0x100>;
247 };
248
249 rtic_b: rtic-b@20 {
250 compatible = "fsl,sec-v5.4-rtic-memory",
251 "fsl,sec-v5.0-rtic-memory",
252 "fsl,sec-v4.0-rtic-memory";
253 reg = <0x20 0x20>, <0x200 0x100>;
254 };
255
256 rtic_c: rtic-c@40 {
257 compatible = "fsl,sec-v5.4-rtic-memory",
258 "fsl,sec-v5.0-rtic-memory",
259 "fsl,sec-v4.0-rtic-memory";
260 reg = <0x40 0x20>, <0x300 0x100>;
261 };
262
263 rtic_d: rtic-d@60 {
264 compatible = "fsl,sec-v5.4-rtic-memory",
265 "fsl,sec-v5.0-rtic-memory",
266 "fsl,sec-v4.0-rtic-memory";
267 reg = <0x60 0x20>, <0x400 0x100>;
268 };
269 };
270 };
271
272 sfp: efuse@1e80000 {
273 compatible = "fsl,ls1021a-sfp";
274 reg = <0x0 0x1e80000 0x0 0x10000>;
275 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
276 QORIQ_CLK_PLL_DIV(4)>;
277 clock-names = "sfp";
278 };
279
280 sec_mon: sec_mon@1e90000 {
281 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
282 "fsl,sec-v4.0-mon";
283 reg = <0x0 0x1e90000 0x0 0x10000>;
284 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
286 };
287
288 dcfg: dcfg@1ee0000 {
289 compatible = "fsl,ls1012a-dcfg",
290 "syscon";
291 reg = <0x0 0x1ee0000 0x0 0x1000>;
292 big-endian;
293 };
294
295 clockgen: clocking@1ee1000 {
296 compatible = "fsl,ls1012a-clockgen";
297 reg = <0x0 0x1ee1000 0x0 0x1000>;
298 #clock-cells = <2>;
299 clocks = <&sysclk &coreclk>;
300 clock-names = "sysclk", "coreclk";
301 };
302
303 tmu: tmu@1f00000 {
304 compatible = "fsl,qoriq-tmu";
305 reg = <0x0 0x1f00000 0x0 0x10000>;
306 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
307 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
308 fsl,tmu-calibration =
309 <0x00000000 0x00000025>,
310 <0x00000001 0x0000002c>,
311 <0x00000002 0x00000032>,
312 <0x00000003 0x00000039>,
313 <0x00000004 0x0000003f>,
314 <0x00000005 0x00000046>,
315 <0x00000006 0x0000004c>,
316 <0x00000007 0x00000053>,
317 <0x00000008 0x00000059>,
318 <0x00000009 0x0000005f>,
319 <0x0000000a 0x00000066>,
320 <0x0000000b 0x0000006c>,
321
322 <0x00010000 0x00000026>,
323 <0x00010001 0x0000002d>,
324 <0x00010002 0x00000035>,
325 <0x00010003 0x0000003d>,
326 <0x00010004 0x00000045>,
327 <0x00010005 0x0000004d>,
328 <0x00010006 0x00000055>,
329 <0x00010007 0x0000005d>,
330 <0x00010008 0x00000065>,
331 <0x00010009 0x0000006d>,
332
333 <0x00020000 0x00000026>,
334 <0x00020001 0x00000030>,
335 <0x00020002 0x0000003a>,
336 <0x00020003 0x00000044>,
337 <0x00020004 0x0000004e>,
338 <0x00020005 0x00000059>,
339 <0x00020006 0x00000063>,
340
341 <0x00030000 0x00000014>,
342 <0x00030001 0x00000021>,
343 <0x00030002 0x0000002e>,
344 <0x00030003 0x0000003a>,
345 <0x00030004 0x00000047>,
346 <0x00030005 0x00000053>,
347 <0x00030006 0x00000060>;
348 #thermal-sensor-cells = <1>;
349 };
350
351 i2c0: i2c@2180000 {
352 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <0x0 0x2180000 0x0 0x10000>;
356 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
358 QORIQ_CLK_PLL_DIV(4)>;
359 scl-gpios = <&gpio0 2 0>;
360 status = "disabled";
361 };
362
363 i2c1: i2c@2190000 {
364 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 reg = <0x0 0x2190000 0x0 0x10000>;
368 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
370 QORIQ_CLK_PLL_DIV(4)>;
371 scl-gpios = <&gpio0 13 0>;
372 status = "disabled";
373 };
374
375 dspi: spi@2100000 {
376 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 reg = <0x0 0x2100000 0x0 0x10000>;
380 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
381 clock-names = "dspi";
382 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
383 QORIQ_CLK_PLL_DIV(1)>;
384 spi-num-chipselects = <5>;
385 big-endian;
386 status = "disabled";
387 };
388
389 duart0: serial@21c0500 {
390 compatible = "fsl,ns16550", "ns16550a";
391 reg = <0x00 0x21c0500 0x0 0x100>;
392 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
394 QORIQ_CLK_PLL_DIV(1)>;
395 status = "disabled";
396 };
397
398 duart1: serial@21c0600 {
399 compatible = "fsl,ns16550", "ns16550a";
400 reg = <0x00 0x21c0600 0x0 0x100>;
401 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
403 QORIQ_CLK_PLL_DIV(1)>;
404 status = "disabled";
405 };
406
407 gpio0: gpio@2300000 {
408 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
409 reg = <0x0 0x2300000 0x0 0x10000>;
410 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 };
416
417 gpio1: gpio@2310000 {
418 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
419 reg = <0x0 0x2310000 0x0 0x10000>;
420 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
421 gpio-controller;
422 #gpio-cells = <2>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 };
426
427 wdog0: watchdog@2ad0000 {
428 compatible = "fsl,ls1012a-wdt",
429 "fsl,imx21-wdt";
430 reg = <0x0 0x2ad0000 0x0 0x10000>;
431 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
433 big-endian;
434 };
435
436 sai1: sai@2b50000 {
437 #sound-dai-cells = <0>;
438 compatible = "fsl,vf610-sai";
439 reg = <0x0 0x2b50000 0x0 0x10000>;
440 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
442 QORIQ_CLK_PLL_DIV(4)>,
443 <&clockgen QORIQ_CLK_PLATFORM_PLL
444 QORIQ_CLK_PLL_DIV(4)>,
445 <&clockgen QORIQ_CLK_PLATFORM_PLL
446 QORIQ_CLK_PLL_DIV(4)>,
447 <&clockgen QORIQ_CLK_PLATFORM_PLL
448 QORIQ_CLK_PLL_DIV(4)>;
449 clock-names = "bus", "mclk1", "mclk2", "mclk3";
450 dma-names = "rx", "tx";
451 dmas = <&edma0 1 46>,
452 <&edma0 1 47>;
453 status = "disabled";
454 };
455
456 sai2: sai@2b60000 {
457 #sound-dai-cells = <0>;
458 compatible = "fsl,vf610-sai";
459 reg = <0x0 0x2b60000 0x0 0x10000>;
460 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
462 QORIQ_CLK_PLL_DIV(4)>,
463 <&clockgen QORIQ_CLK_PLATFORM_PLL
464 QORIQ_CLK_PLL_DIV(4)>,
465 <&clockgen QORIQ_CLK_PLATFORM_PLL
466 QORIQ_CLK_PLL_DIV(4)>,
467 <&clockgen QORIQ_CLK_PLATFORM_PLL
468 QORIQ_CLK_PLL_DIV(4)>;
469 clock-names = "bus", "mclk1", "mclk2", "mclk3";
470 dma-names = "rx", "tx";
471 dmas = <&edma0 1 44>,
472 <&edma0 1 45>;
473 status = "disabled";
474 };
475
476 edma0: dma-controller@2c00000 {
477 #dma-cells = <2>;
478 compatible = "fsl,vf610-edma";
479 reg = <0x0 0x2c00000 0x0 0x10000>,
480 <0x0 0x2c10000 0x0 0x10000>,
481 <0x0 0x2c20000 0x0 0x10000>;
482 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "edma-tx", "edma-err";
485 dma-channels = <32>;
486 big-endian;
487 clock-names = "dmamux0", "dmamux1";
488 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
489 QORIQ_CLK_PLL_DIV(4)>,
490 <&clockgen QORIQ_CLK_PLATFORM_PLL
491 QORIQ_CLK_PLL_DIV(4)>;
492 };
493
494 usb0: usb@2f00000 {
495 compatible = "snps,dwc3";
496 reg = <0x0 0x2f00000 0x0 0x10000>;
497 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
498 dr_mode = "host";
499 snps,quirk-frame-length-adjustment = <0x20>;
500 snps,dis_rxdet_inp3_quirk;
501 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
502 };
503
504 sata: sata@3200000 {
505 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
506 reg = <0x0 0x3200000 0x0 0x10000>,
507 <0x0 0x20140520 0x0 0x4>;
508 reg-names = "ahci", "sata-ecc";
509 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
511 QORIQ_CLK_PLL_DIV(1)>;
512 dma-coherent;
513 status = "disabled";
514 };
515
516 usb1: usb@8600000 {
517 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
518 reg = <0x0 0x8600000 0x0 0x1000>;
519 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
520 dr_mode = "host";
521 phy_type = "ulpi";
522 };
523
524 msi: msi-controller1@1572000 {
525 compatible = "fsl,ls1012a-msi";
526 reg = <0x0 0x1572000 0x0 0x8>;
527 msi-controller;
528 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
529 };
530
531 pcie1: pcie@3400000 {
532 compatible = "fsl,ls1012a-pcie";
533 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
534 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
535 reg-names = "regs", "config";
536 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
537 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
538 interrupt-names = "pme", "aer";
539 #address-cells = <3>;
540 #size-cells = <2>;
541 device_type = "pci";
542 bus-range = <0x0 0xff>;
543 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
544 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
545 msi-parent = <&msi>;
546 #interrupt-cells = <1>;
547 interrupt-map-mask = <0 0 0 7>;
548 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
549 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
550 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
551 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
552 big-endian;
553 status = "disabled";
554 };
555
556 rcpm: wakeup-controller@1ee2140 {
557 compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
558 reg = <0x0 0x1ee2140 0x0 0x4>;
559 #fsl,rcpm-wakeup-cells = <1>;
560 };
561
562 ftm_alarm0: rtc@29d0000 {
563 compatible = "fsl,ls1012a-ftm-alarm";
564 reg = <0x0 0x29d0000 0x0 0x10000>;
565 fsl,rcpm-wakeup = <&rcpm 0x20000>;
566 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
567 big-endian;
568 };
569 };
570
571 firmware {
572 optee {
573 compatible = "linaro,optee-tz";
574 method = "smc";
575 };
576 };
577 };
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