1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree fragment for LS1028A QDS board, serdes 13bb
4 *
5 * Copyright 2019-2021 NXP
6 *
7 * Requires a LS1028A QDS board with lane B rework.
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
10 */
11
12 /dts-v1/;
13 /plugin/;
14
15 &mdio_slot1 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 slot1_sgmii: ethernet-phy@2 {
20 /* AQR112 */
21 reg = <0x2>;
22 compatible = "ethernet-phy-ieee802.3-c45";
23 };
24 };
25
26 &enetc_port0 {
27 phy-handle = <&slot1_sgmii>;
28 phy-mode = "usxgmii";
29 managed = "in-band-status";
30 status = "okay";
31 };
32
33 &mdio_slot2 {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 /* 4 ports on AQR412 */
38 slot2_qxgmii0: ethernet-phy@0 {
39 reg = <0x0>;
40 compatible = "ethernet-phy-ieee802.3-c45";
41 };
42
43 slot2_qxgmii1: ethernet-phy@1 {
44 reg = <0x1>;
45 compatible = "ethernet-phy-ieee802.3-c45";
46 };
47
48 slot2_qxgmii2: ethernet-phy@2 {
49 reg = <0x2>;
50 compatible = "ethernet-phy-ieee802.3-c45";
51 };
52
53 slot2_qxgmii3: ethernet-phy@3 {
54 reg = <0x3>;
55 compatible = "ethernet-phy-ieee802.3-c45";
56 };
57 };
58
59 &mscc_felix_ports {
60 port@0 {
61 status = "okay";
62 phy-handle = <&slot2_qxgmii0>;
63 phy-mode = "usxgmii";
64 managed = "in-band-status";
65 };
66
67 port@1 {
68 status = "okay";
69 phy-handle = <&slot2_qxgmii1>;
70 phy-mode = "usxgmii";
71 managed = "in-band-status";
72 };
73
74 port@2 {
75 status = "okay";
76 phy-handle = <&slot2_qxgmii2>;
77 phy-mode = "usxgmii";
78 managed = "in-band-status";
79 };
80
81 port@3 {
82 status = "okay";
83 phy-handle = <&slot2_qxgmii3>;
84 phy-mode = "usxgmii";
85 managed = "in-band-status";
86 };
87 };
88
89 &mscc_felix {
90 status = "okay";
91 };
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