1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
13
14 / {
15 model = "LS1043A RDB Board";
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
17
18 aliases {
19 serial0 = &duart0;
20 serial1 = &duart1;
21 serial2 = &duart2;
22 serial3 = &duart3;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28 };
29
30 &i2c0 {
31 status = "okay";
32
33 ina220@40 {
34 compatible = "ti,ina220";
35 reg = <0x40>;
36 shunt-resistor = <1000>;
37 };
38
39 adt7461a@4c {
40 compatible = "adi,adt7461";
41 reg = <0x4c>;
42 };
43
44 rtc@51 {
45 compatible = "nxp,pcf85263";
46 reg = <0x51>;
47 };
48
49 eeprom@52 {
50 compatible = "atmel,24c512";
51 reg = <0x52>;
52 };
53
54 eeprom@53 {
55 compatible = "atmel,24c512";
56 reg = <0x53>;
57 };
58
59 rtc@68 {
60 compatible = "pericom,pt7c4338";
61 reg = <0x68>;
62 };
63 };
64
65 &ifc {
66 status = "okay";
67 #address-cells = <2>;
68 #size-cells = <1>;
69 /* NOR, NAND Flashes and FPGA on board */
70 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
71 0x1 0x0 0x0 0x7e800000 0x00010000
72 0x2 0x0 0x0 0x7fb00000 0x00000100>;
73
74 flash@0,0 {
75 compatible = "cfi-flash";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x0 0x0 0x8000000>;
79 big-endian;
80 bank-width = <2>;
81 device-width = <1>;
82 };
83
84 nand@1,0 {
85 compatible = "fsl,ifc-nand";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x1 0x0 0x10000>;
89 };
90
91 cpld: board-control@2,0 {
92 compatible = "fsl,ls1043ardb-cpld";
93 reg = <0x2 0x0 0x0000100>;
94 };
95 };
96
97 &dspi0 {
98 bus-num = <0>;
99 status = "okay";
100
101 flash@0 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
105 reg = <0>;
106 spi-max-frequency = <1000000>; /* input clock */
107 /*
108 * Standard CS timing properties replace the deprecated vendor
109 * variants below.
110 */
111 spi-cs-setup-delay-ns = <100>;
112 spi-cs-hold-delay-ns = <100>;
113 fsl,spi-cs-sck-delay = <100>;
114 fsl,spi-sck-cs-delay = <100>;
115 };
116
117 slic@2 {
118 compatible = "maxim,ds26522";
119 reg = <2>;
120 spi-max-frequency = <2000000>;
121 /*
122 * Standard CS timing properties replace the deprecated vendor
123 * variants below.
124 */
125 spi-cs-setup-delay-ns = <100>;
126 spi-cs-hold-delay-ns = <50>;
127 fsl,spi-cs-sck-delay = <100>;
128 fsl,spi-sck-cs-delay = <50>;
129 };
130
131 slic@3 {
132 compatible = "maxim,ds26522";
133 reg = <3>;
134 spi-max-frequency = <2000000>;
135 /*
136 * Standard CS timing properties replace the deprecated vendor
137 * variants below.
138 */
139 spi-cs-setup-delay-ns = <100>;
140 spi-cs-hold-delay-ns = <50>;
141 fsl,spi-cs-sck-delay = <100>;
142 fsl,spi-sck-cs-delay = <50>;
143 };
144 };
145
146 &duart0 {
147 status = "okay";
148 };
149
150 &duart1 {
151 status = "okay";
152 };
153
154 #include "fsl-ls1043-post.dtsi"
155
156 &fman0 {
157 ethernet@e0000 {
158 phy-handle = <&qsgmii_phy1>;
159 phy-connection-type = "qsgmii";
160 };
161
162 ethernet@e2000 {
163 phy-handle = <&qsgmii_phy2>;
164 phy-connection-type = "qsgmii";
165 };
166
167 ethernet@e4000 {
168 phy-handle = <&rgmii_phy1>;
169 phy-connection-type = "rgmii-id";
170 };
171
172 ethernet@e6000 {
173 phy-handle = <&rgmii_phy2>;
174 phy-connection-type = "rgmii-id";
175 };
176
177 ethernet@e8000 {
178 phy-handle = <&qsgmii_phy3>;
179 phy-connection-type = "qsgmii";
180 };
181
182 ethernet@ea000 {
183 phy-handle = <&qsgmii_phy4>;
184 phy-connection-type = "qsgmii";
185 };
186
187 ethernet@f0000 { /* 10GEC1 */
188 phy-handle = <&aqr105_phy>;
189 phy-connection-type = "xgmii";
190 };
191
192 mdio@fc000 {
193 rgmii_phy1: ethernet-phy@1 {
194 reg = <0x1>;
195 };
196
197 rgmii_phy2: ethernet-phy@2 {
198 reg = <0x2>;
199 };
200
201 qsgmii_phy1: ethernet-phy@4 {
202 reg = <0x4>;
203 };
204
205 qsgmii_phy2: ethernet-phy@5 {
206 reg = <0x5>;
207 };
208
209 qsgmii_phy3: ethernet-phy@6 {
210 reg = <0x6>;
211 };
212
213 qsgmii_phy4: ethernet-phy@7 {
214 reg = <0x7>;
215 };
216 };
217
218 mdio@fd000 {
219 aqr105_phy: ethernet-phy@1 {
220 compatible = "ethernet-phy-ieee802.3-c45";
221 interrupts = <0 132 4>;
222 reg = <0x1>;
223 };
224 };
225 };
226
227 &uqe {
228 ucc_hdlc: ucc@2000 {
229 compatible = "fsl,ucc-hdlc";
230 rx-clock-name = "clk8";
231 tx-clock-name = "clk9";
232 fsl,rx-sync-clock = "rsync_pin";
233 fsl,tx-sync-clock = "tsync_pin";
234 fsl,tx-timeslot-mask = <0xfffffffe>;
235 fsl,rx-timeslot-mask = <0xfffffffe>;
236 fsl,tdm-framer-type = "e1";
237 fsl,tdm-id = <0>;
238 fsl,siram-entry-id = <0>;
239 fsl,tdm-interface;
240 };
241 };
242
243 &usb0 {
244 status = "okay";
245 };
246
247 &usb1 {
248 status = "okay";
249 };
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