1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
15
16 / {
17 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 crypto = &crypto;
24 fman0 = &fman0;
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 ethernet4 = &enet4;
30 ethernet5 = &enet5;
31 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 /*
40 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, which will fill this in.
42 *
43 * Currently supported enable-method is psci v0.2
44 */
45 cpu0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
50 next-level-cache = <&l2>;
51 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53";
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 next-level-cache = <&l2>;
61 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>;
63 };
64
65 cpu2: cpu@2 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53";
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
70 next-level-cache = <&l2>;
71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>;
73 };
74
75 cpu3: cpu@3 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53";
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
80 next-level-cache = <&l2>;
81 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>;
83 };
84
85 l2: l2-cache {
86 compatible = "cache";
87 cache-level = <2>;
88 cache-unified;
89 };
90 };
91
92 idle-states {
93 /*
94 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to use PSCI.
96 */
97 entry-method = "psci";
98
99 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle-state";
101 idle-state-name = "PH20";
102 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <1000>;
104 exit-latency-us = <1000>;
105 min-residency-us = <3000>;
106 };
107 };
108
109 memory@80000000 {
110 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2GiB DRAM */
113 };
114
115 reserved-memory {
116 #address-cells = <2>;
117 #size-cells = <2>;
118 ranges;
119
120 bman_fbpr: bman-fbpr {
121 compatible = "shared-dma-pool";
122 size = <0 0x1000000>;
123 alignment = <0 0x1000000>;
124 no-map;
125 };
126
127 qman_fqd: qman-fqd {
128 compatible = "shared-dma-pool";
129 size = <0 0x400000>;
130 alignment = <0 0x400000>;
131 no-map;
132 };
133
134 qman_pfdr: qman-pfdr {
135 compatible = "shared-dma-pool";
136 size = <0 0x2000000>;
137 alignment = <0 0x2000000>;
138 no-map;
139 };
140 };
141
142 sysclk: sysclk {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <100000000>;
146 clock-output-names = "sysclk";
147 };
148
149 reboot {
150 compatible = "syscon-reboot";
151 regmap = <&dcfg>;
152 offset = <0xb0>;
153 mask = <0x02>;
154 };
155
156 thermal-zones {
157 ddr-thermal {
158 polling-delay-passive = <1000>;
159 polling-delay = <5000>;
160 thermal-sensors = <&tmu 0>;
161
162 trips {
163 ddr-ctrler-alert {
164 temperature = <85000>;
165 hysteresis = <2000>;
166 type = "passive";
167 };
168
169 ddr-ctrler-crit {
170 temperature = <95000>;
171 hysteresis = <2000>;
172 type = "critical";
173 };
174 };
175 };
176
177 serdes-thermal {
178 polling-delay-passive = <1000>;
179 polling-delay = <5000>;
180 thermal-sensors = <&tmu 1>;
181
182 trips {
183 serdes-alert {
184 temperature = <85000>;
185 hysteresis = <2000>;
186 type = "passive";
187 };
188
189 serdes-crit {
190 temperature = <95000>;
191 hysteresis = <2000>;
192 type = "critical";
193 };
194 };
195 };
196
197 fman-thermal {
198 polling-delay-passive = <1000>;
199 polling-delay = <5000>;
200 thermal-sensors = <&tmu 2>;
201
202 trips {
203 fman-alert {
204 temperature = <85000>;
205 hysteresis = <2000>;
206 type = "passive";
207 };
208
209 fman-crit {
210 temperature = <95000>;
211 hysteresis = <2000>;
212 type = "critical";
213 };
214 };
215 };
216
217 cluster-thermal {
218 polling-delay-passive = <1000>;
219 polling-delay = <5000>;
220 thermal-sensors = <&tmu 3>;
221
222 trips {
223 core_cluster_alert: core-cluster-alert {
224 temperature = <85000>;
225 hysteresis = <2000>;
226 type = "passive";
227 };
228
229 core_cluster_crit: core-cluster-crit {
230 temperature = <95000>;
231 hysteresis = <2000>;
232 type = "critical";
233 };
234 };
235
236 cooling-maps {
237 map0 {
238 trip = <&core_cluster_alert>;
239 cooling-device =
240 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
241 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
242 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
243 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 };
245 };
246 };
247
248 sec-thermal {
249 polling-delay-passive = <1000>;
250 polling-delay = <5000>;
251 thermal-sensors = <&tmu 4>;
252
253 trips {
254 sec-alert {
255 temperature = <85000>;
256 hysteresis = <2000>;
257 type = "passive";
258 };
259
260 sec-crit {
261 temperature = <95000>;
262 hysteresis = <2000>;
263 type = "critical";
264 };
265 };
266 };
267 };
268
269 timer {
270 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
272 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
273 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
274 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
275 fsl,erratum-a008585;
276 };
277
278 pmu {
279 compatible = "arm,cortex-a53-pmu";
280 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-affinity = <&cpu0>,
285 <&cpu1>,
286 <&cpu2>,
287 <&cpu3>;
288 };
289
290 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400";
292 #interrupt-cells = <3>;
293 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
299 };
300
301 soc: soc {
302 compatible = "simple-bus";
303 #address-cells = <2>;
304 #size-cells = <2>;
305 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
307 dma-coherent;
308
309 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>;
313 clocks = <&sysclk>;
314 };
315
316 scfg: scfg@1570000 {
317 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian;
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0x0 0x0 0x1570000 0x10000>;
323
324 extirq: interrupt-controller@1ac {
325 compatible = "fsl,ls1043a-extirq";
326 #interrupt-cells = <2>;
327 #address-cells = <0>;
328 interrupt-controller;
329 reg = <0x1ac 4>;
330 interrupt-map =
331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map-mask = <0xf 0x0>;
344 };
345 };
346
347 crypto: crypto@1700000 {
348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec-v4.0";
350 fsl,sec-era = <3>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
356 dma-coherent;
357
358 sec_jr0: jr@10000 {
359 compatible = "fsl,sec-v5.4-job-ring",
360 "fsl,sec-v5.0-job-ring",
361 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 0x10000>;
363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
364 };
365
366 sec_jr1: jr@20000 {
367 compatible = "fsl,sec-v5.4-job-ring",
368 "fsl,sec-v5.0-job-ring",
369 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 0x10000>;
371 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
372 };
373
374 sec_jr2: jr@30000 {
375 compatible = "fsl,sec-v5.4-job-ring",
376 "fsl,sec-v5.0-job-ring",
377 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 0x10000>;
379 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
380 };
381
382 sec_jr3: jr@40000 {
383 compatible = "fsl,sec-v5.4-job-ring",
384 "fsl,sec-v5.0-job-ring",
385 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 0x10000>;
387 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
388 };
389 };
390
391 sfp: efuse@1e80000 {
392 compatible = "fsl,ls1021a-sfp";
393 reg = <0x0 0x1e80000 0x0 0x10000>;
394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
395 QORIQ_CLK_PLL_DIV(4)>;
396 clock-names = "sfp";
397 };
398
399 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0x0 0x1000>;
402 big-endian;
403 };
404
405 ifc: memory-controller@1530000 {
406 compatible = "fsl,ifc";
407 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
409 };
410
411 qspi: spi@1550000 {
412 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
419 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QORIQ_CLK_PLL_DIV(1)>,
422 <&clockgen QORIQ_CLK_PLATFORM_PLL
423 QORIQ_CLK_PLL_DIV(1)>;
424 status = "disabled";
425 };
426
427 esdhc: mmc@1560000 {
428 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
431 clock-frequency = <0>;
432 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12;
434 bus-width = <4>;
435 };
436
437 ddr: memory-controller@1080000 {
438 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
441 };
442
443 tmu: tmu@1f00000 {
444 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
447 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration =
449 <0x00000000 0x00000023>,
450 <0x00000001 0x0000002a>,
451 <0x00000002 0x00000031>,
452 <0x00000003 0x00000037>,
453 <0x00000004 0x0000003e>,
454 <0x00000005 0x00000044>,
455 <0x00000006 0x0000004b>,
456 <0x00000007 0x00000051>,
457 <0x00000008 0x00000058>,
458 <0x00000009 0x0000005e>,
459 <0x0000000a 0x00000065>,
460 <0x0000000b 0x0000006b>,
461
462 <0x00010000 0x00000023>,
463 <0x00010001 0x0000002b>,
464 <0x00010002 0x00000033>,
465 <0x00010003 0x0000003b>,
466 <0x00010004 0x00000043>,
467 <0x00010005 0x0000004b>,
468 <0x00010006 0x00000054>,
469 <0x00010007 0x0000005c>,
470 <0x00010008 0x00000064>,
471 <0x00010009 0x0000006c>,
472
473 <0x00020000 0x00000021>,
474 <0x00020001 0x0000002c>,
475 <0x00020002 0x00000036>,
476 <0x00020003 0x00000040>,
477 <0x00020004 0x0000004b>,
478 <0x00020005 0x00000055>,
479 <0x00020006 0x0000005f>,
480
481 <0x00030000 0x00000013>,
482 <0x00030001 0x0000001d>,
483 <0x00030002 0x00000028>,
484 <0x00030003 0x00000032>,
485 <0x00030004 0x0000003d>,
486 <0x00030005 0x00000047>,
487 <0x00030006 0x00000052>,
488 <0x00030007 0x0000005c>;
489 #thermal-sensor-cells = <1>;
490 };
491
492 qman: qman@1880000 {
493 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman_fqd &qman_pfdr>;
497 };
498
499 bman: bman@1890000 {
500 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman_fbpr>;
504 };
505
506 bportals: bman-portals-bus@508000000 {
507 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 };
509
510 qportals: qman-portals-bus@500000000 {
511 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 };
513
514 dspi0: spi@2100000 {
515 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
520 clock-names = "dspi";
521 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
522 QORIQ_CLK_PLL_DIV(1)>;
523 spi-num-chipselects = <5>;
524 big-endian;
525 status = "disabled";
526 };
527
528 i2c0: i2c@2180000 {
529 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
534 clock-names = "ipg";
535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
536 QORIQ_CLK_PLL_DIV(1)>;
537 dmas = <&edma0 1 38>,
538 <&edma0 1 39>;
539 dma-names = "rx", "tx";
540 status = "disabled";
541 };
542
543 i2c1: i2c@2190000 {
544 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
545 #address-cells = <1>;
546 #size-cells = <0>;
547 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
549 clock-names = "ipg";
550 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
551 QORIQ_CLK_PLL_DIV(1)>;
552 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
553 status = "disabled";
554 };
555
556 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
562 clock-names = "ipg";
563 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564 QORIQ_CLK_PLL_DIV(1)>;
565 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
566 status = "disabled";
567 };
568
569 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
575 clock-names = "ipg";
576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
577 QORIQ_CLK_PLL_DIV(1)>;
578 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 status = "disabled";
580 };
581
582 duart0: serial@21c0500 {
583 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
587 QORIQ_CLK_PLL_DIV(1)>;
588 };
589
590 duart1: serial@21c0600 {
591 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
595 QORIQ_CLK_PLL_DIV(1)>;
596 };
597
598 duart2: serial@21d0500 {
599 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
603 QORIQ_CLK_PLL_DIV(1)>;
604 };
605
606 duart3: serial@21d0600 {
607 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
611 QORIQ_CLK_PLL_DIV(1)>;
612 };
613
614 gpio1: gpio@2300000 {
615 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
618 gpio-controller;
619 #gpio-cells = <2>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 };
623
624 gpio2: gpio@2310000 {
625 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
628 gpio-controller;
629 #gpio-cells = <2>;
630 interrupt-controller;
631 #interrupt-cells = <2>;
632 };
633
634 gpio3: gpio@2320000 {
635 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
638 gpio-controller;
639 #gpio-cells = <2>;
640 interrupt-controller;
641 #interrupt-cells = <2>;
642 };
643
644 gpio4: gpio@2330000 {
645 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
648 gpio-controller;
649 #gpio-cells = <2>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
652 };
653
654 uqe: uqe-bus@2400000 {
655 #address-cells = <1>;
656 #size-cells = <1>;
657 compatible = "fsl,qe", "simple-bus";
658 ranges = <0x0 0x0 0x2400000 0x40000>;
659 reg = <0x0 0x2400000 0x0 0x480>;
660 brg-frequency = <100000000>;
661 bus-frequency = <200000000>;
662 fsl,qe-num-riscs = <1>;
663 fsl,qe-num-snums = <28>;
664
665 qeic: qeic@80 {
666 compatible = "fsl,qe-ic";
667 reg = <0x80 0x80>;
668 interrupt-controller;
669 #interrupt-cells = <1>;
670 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
672 };
673
674 si1: si@700 {
675 compatible = "fsl,ls1043-qe-si",
676 "fsl,t1040-qe-si";
677 reg = <0x700 0x80>;
678 };
679
680 siram1: siram@1000 {
681 compatible = "fsl,ls1043-qe-siram",
682 "fsl,t1040-qe-siram";
683 reg = <0x1000 0x800>;
684 };
685
686 ucc@2000 {
687 cell-index = <1>;
688 reg = <0x2000 0x200>;
689 interrupts = <32>;
690 interrupt-parent = <&qeic>;
691 };
692
693 ucc@2200 {
694 cell-index = <3>;
695 reg = <0x2200 0x200>;
696 interrupts = <34>;
697 interrupt-parent = <&qeic>;
698 };
699
700 muram@10000 {
701 #address-cells = <1>;
702 #size-cells = <1>;
703 compatible = "fsl,qe-muram", "fsl,cpm-muram";
704 ranges = <0x0 0x10000 0x6000>;
705
706 data-only@0 {
707 compatible = "fsl,qe-muram-data",
708 "fsl,cpm-muram-data";
709 reg = <0x0 0x6000>;
710 };
711 };
712 };
713
714 lpuart0: serial@2950000 {
715 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
719 clock-names = "ipg";
720 status = "disabled";
721 };
722
723 lpuart1: serial@2960000 {
724 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
728 QORIQ_CLK_PLL_DIV(1)>;
729 clock-names = "ipg";
730 status = "disabled";
731 };
732
733 lpuart2: serial@2970000 {
734 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
738 QORIQ_CLK_PLL_DIV(1)>;
739 clock-names = "ipg";
740 status = "disabled";
741 };
742
743 lpuart3: serial@2980000 {
744 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
748 QORIQ_CLK_PLL_DIV(1)>;
749 clock-names = "ipg";
750 status = "disabled";
751 };
752
753 lpuart4: serial@2990000 {
754 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
758 QORIQ_CLK_PLL_DIV(1)>;
759 clock-names = "ipg";
760 status = "disabled";
761 };
762
763 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
768 QORIQ_CLK_PLL_DIV(1)>;
769 clock-names = "ipg";
770 status = "disabled";
771 };
772
773 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
778 QORIQ_CLK_PLL_DIV(1)>;
779 big-endian;
780 };
781
782 edma0: dma-controller@2c00000 {
783 #dma-cells = <2>;
784 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>;
792 big-endian;
793 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
795 QORIQ_CLK_PLL_DIV(1)>,
796 <&clockgen QORIQ_CLK_PLATFORM_PLL
797 QORIQ_CLK_PLL_DIV(1)>;
798 };
799
800 aux_bus: bus {
801 #address-cells = <2>;
802 #size-cells = <2>;
803 compatible = "simple-bus";
804 ranges;
805 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
806
807 usb0: usb@2f00000 {
808 compatible = "snps,dwc3";
809 reg = <0x0 0x2f00000 0x0 0x10000>;
810 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
811 dr_mode = "host";
812 snps,quirk-frame-length-adjustment = <0x20>;
813 snps,dis_rxdet_inp3_quirk;
814 usb3-lpm-capable;
815 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
816 status = "disabled";
817 };
818
819 usb1: usb@3000000 {
820 compatible = "snps,dwc3";
821 reg = <0x0 0x3000000 0x0 0x10000>;
822 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
823 dr_mode = "host";
824 snps,quirk-frame-length-adjustment = <0x20>;
825 snps,dis_rxdet_inp3_quirk;
826 usb3-lpm-capable;
827 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
828 status = "disabled";
829 };
830
831 usb2: usb@3100000 {
832 compatible = "snps,dwc3";
833 reg = <0x0 0x3100000 0x0 0x10000>;
834 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
835 dr_mode = "host";
836 snps,quirk-frame-length-adjustment = <0x20>;
837 snps,dis_rxdet_inp3_quirk;
838 usb3-lpm-capable;
839 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
840 status = "disabled";
841 };
842
843 sata: sata@3200000 {
844 compatible = "fsl,ls1043a-ahci";
845 reg = <0x0 0x3200000 0x0 0x10000>,
846 <0x0 0x20140520 0x0 0x4>;
847 reg-names = "ahci", "sata-ecc";
848 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
850 QORIQ_CLK_PLL_DIV(1)>;
851 dma-coherent;
852 };
853 };
854
855 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller;
859 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
860 };
861
862 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller;
866 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
867 };
868
869 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller;
873 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
874 };
875
876 pcie1: pcie@3400000 {
877 compatible = "fsl,ls1043a-pcie";
878 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
879 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "config";
881 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
883 interrupt-names = "pme", "aer";
884 #address-cells = <3>;
885 #size-cells = <2>;
886 device_type = "pci";
887 num-viewport = <6>;
888 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1>;
893 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg 0>;
899 big-endian;
900 status = "disabled";
901 };
902
903 pcie2: pcie@3500000 {
904 compatible = "fsl,ls1043a-pcie";
905 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
906 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "config";
908 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
910 interrupt-names = "pme", "aer";
911 #address-cells = <3>;
912 #size-cells = <2>;
913 device_type = "pci";
914 num-viewport = <6>;
915 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1>;
920 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg 1>;
926 big-endian;
927 status = "disabled";
928 };
929
930 pcie3: pcie@3600000 {
931 compatible = "fsl,ls1043a-pcie";
932 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
933 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "config";
935 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
937 interrupt-names = "pme", "aer";
938 #address-cells = <3>;
939 #size-cells = <2>;
940 device_type = "pci";
941 num-viewport = <6>;
942 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1>;
947 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg 2>;
953 big-endian;
954 status = "disabled";
955 };
956
957 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls1043a-qdma", "fsl,ls1021a-qdma";
959 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
960 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
961 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
962 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", "qdma-queue2", "qdma-queue3";
969 #dma-cells = <1>;
970 dma-channels = <8>;
971 block-number = <1>;
972 block-offset = <0x10000>;
973 fsl,dma-queues = <2>;
974 status-sizes = <64>;
975 queue-sizes = <64 64>;
976 big-endian;
977 };
978
979 rcpm: wakeup-controller@1ee2140 {
980 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
981 reg = <0x0 0x1ee2140 0x0 0x4>;
982 #fsl,rcpm-wakeup-cells = <1>;
983 };
984
985 ftm_alarm0: rtc@29d0000 {
986 compatible = "fsl,ls1043a-ftm-alarm";
987 reg = <0x0 0x29d0000 0x0 0x10000>;
988 fsl,rcpm-wakeup = <&rcpm 0x20000>;
989 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
990 big-endian;
991 };
992 };
993
994 firmware {
995 optee {
996 compatible = "linaro,optee-tz";
997 method = "smc";
998 };
999 };
1000
1001 };
1002
1003 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi"
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