1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2019 NXP.
6 *
7 */
8
9 /dts-v1/;
10
11 #include "fsl-ls1046a.dtsi"
12
13 / {
14 model = "LS1046A FRWY Board";
15 compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
16
17 aliases {
18 serial0 = &duart0;
19 serial1 = &duart1;
20 serial2 = &duart2;
21 serial3 = &duart3;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 sb_3v3: regulator-sb3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "LT8642SEV-3.3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-boot-on;
34 regulator-always-on;
35 };
36 };
37
38 &duart0 {
39 status = "okay";
40 };
41
42 &duart1 {
43 status = "okay";
44 };
45
46 &duart2 {
47 status = "okay";
48 };
49
50 &duart3 {
51 status = "okay";
52 };
53
54 &i2c0 {
55 status = "okay";
56
57 i2c-mux@77 {
58 compatible = "nxp,pca9546";
59 reg = <0x77>;
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 i2c@0 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 reg = <0>;
67
68 power-monitor@40 {
69 compatible = "ti,ina220";
70 reg = <0x40>;
71 shunt-resistor = <1000>;
72 };
73
74 temperature-sensor@4c {
75 compatible = "nxp,sa56004";
76 reg = <0x4c>;
77 vcc-supply = <&sb_3v3>;
78 };
79
80 rtc@51 {
81 compatible = "nxp,pcf2129";
82 reg = <0x51>;
83 };
84
85 eeprom@52 {
86 compatible = "onnn,cat24c04", "atmel,24c04";
87 reg = <0x52>;
88 };
89 };
90 };
91 };
92
93 &ifc {
94 #address-cells = <2>;
95 #size-cells = <1>;
96 /* NAND Flash */
97 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
98 status = "okay";
99
100 nand@0,0 {
101 compatible = "fsl,ifc-nand";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <0x0 0x0 0x10000>;
105 };
106
107 };
108
109 &qspi {
110 status = "okay";
111
112 mt25qu512a0: flash@0 {
113 compatible = "jedec,spi-nor";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 spi-max-frequency = <50000000>;
117 spi-rx-bus-width = <4>;
118 spi-tx-bus-width = <1>;
119 reg = <0>;
120 };
121 };
122
123 #include "fsl-ls1046-post.dtsi"
124
125 &fman0 {
126 ethernet@e0000 {
127 phy-handle = <&qsgmii_phy4>;
128 phy-connection-type = "qsgmii";
129 };
130
131 ethernet@e8000 {
132 phy-handle = <&qsgmii_phy2>;
133 phy-connection-type = "qsgmii";
134 };
135
136 ethernet@ea000 {
137 phy-handle = <&qsgmii_phy1>;
138 phy-connection-type = "qsgmii";
139 };
140
141 ethernet@f2000 {
142 phy-handle = <&qsgmii_phy3>;
143 phy-connection-type = "qsgmii";
144 };
145
146 mdio@fd000 {
147 qsgmii_phy1: ethernet-phy@1c {
148 reg = <0x1c>;
149 };
150
151 qsgmii_phy2: ethernet-phy@1d {
152 reg = <0x1d>;
153 };
154
155 qsgmii_phy3: ethernet-phy@1e {
156 reg = <0x1e>;
157 };
158
159 qsgmii_phy4: ethernet-phy@1f {
160 reg = <0x1f>;
161 };
162 };
163 };
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