1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <mingkai.hu@nxp.com>
9 */
10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
15
16 / {
17 compatible = "fsl,ls1046a";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 crypto = &crypto;
24 fman0 = &fman0;
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 ethernet4 = &enet4;
30 ethernet5 = &enet5;
31 ethernet6 = &enet6;
32 ethernet7 = &enet7;
33 rtc1 = &ftm_alarm0;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a72";
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
45 next-level-cache = <&l2>;
46 cpu-idle-states = <&CPU_PH20>;
47 #cooling-cells = <2>;
48 };
49
50 cpu1: cpu@1 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a72";
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
55 next-level-cache = <&l2>;
56 cpu-idle-states = <&CPU_PH20>;
57 #cooling-cells = <2>;
58 };
59
60 cpu2: cpu@2 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a72";
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
65 next-level-cache = <&l2>;
66 cpu-idle-states = <&CPU_PH20>;
67 #cooling-cells = <2>;
68 };
69
70 cpu3: cpu@3 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a72";
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
75 next-level-cache = <&l2>;
76 cpu-idle-states = <&CPU_PH20>;
77 #cooling-cells = <2>;
78 };
79
80 l2: l2-cache {
81 compatible = "cache";
82 cache-level = <2>;
83 cache-unified;
84 };
85 };
86
87 idle-states {
88 /*
89 * PSCI node is not added default, U-boot will add missing
90 * parts if it determines to use PSCI.
91 */
92 entry-method = "psci";
93
94 CPU_PH20: cpu-ph20 {
95 compatible = "arm,idle-state";
96 idle-state-name = "PH20";
97 arm,psci-suspend-param = <0x0>;
98 entry-latency-us = <1000>;
99 exit-latency-us = <1000>;
100 min-residency-us = <3000>;
101 };
102 };
103
104 memory@80000000 {
105 device_type = "memory";
106 /* Real size will be filled by bootloader */
107 reg = <0x0 0x80000000 0x0 0x0>;
108 };
109
110 sysclk: sysclk {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <100000000>;
114 clock-output-names = "sysclk";
115 };
116
117 reboot {
118 compatible = "syscon-reboot";
119 regmap = <&dcfg>;
120 offset = <0xb0>;
121 mask = <0x02>;
122 };
123
124 thermal-zones {
125 ddr-thermal {
126 polling-delay-passive = <1000>;
127 polling-delay = <5000>;
128 thermal-sensors = <&tmu 0>;
129
130 trips {
131 ddr-ctrler-alert {
132 temperature = <85000>;
133 hysteresis = <2000>;
134 type = "passive";
135 };
136
137 ddr-ctrler-crit {
138 temperature = <95000>;
139 hysteresis = <2000>;
140 type = "critical";
141 };
142 };
143 };
144
145 serdes-thermal {
146 polling-delay-passive = <1000>;
147 polling-delay = <5000>;
148 thermal-sensors = <&tmu 1>;
149
150 trips {
151 serdes-alert {
152 temperature = <85000>;
153 hysteresis = <2000>;
154 type = "passive";
155 };
156
157 serdes-crit {
158 temperature = <95000>;
159 hysteresis = <2000>;
160 type = "critical";
161 };
162 };
163 };
164
165 fman-thermal {
166 polling-delay-passive = <1000>;
167 polling-delay = <5000>;
168 thermal-sensors = <&tmu 2>;
169
170 trips {
171 fman-alert {
172 temperature = <85000>;
173 hysteresis = <2000>;
174 type = "passive";
175 };
176
177 fman-crit {
178 temperature = <95000>;
179 hysteresis = <2000>;
180 type = "critical";
181 };
182 };
183 };
184
185 cluster-thermal {
186 polling-delay-passive = <1000>;
187 polling-delay = <5000>;
188 thermal-sensors = <&tmu 3>;
189
190 trips {
191 core_cluster_alert: core-cluster-alert {
192 temperature = <85000>;
193 hysteresis = <2000>;
194 type = "passive";
195 };
196
197 core_cluster_crit: core-cluster-crit {
198 temperature = <95000>;
199 hysteresis = <2000>;
200 type = "critical";
201 };
202 };
203
204 cooling-maps {
205 map0 {
206 trip = <&core_cluster_alert>;
207 cooling-device =
208 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 };
213 };
214 };
215
216 sec-thermal {
217 polling-delay-passive = <1000>;
218 polling-delay = <5000>;
219 thermal-sensors = <&tmu 4>;
220
221 trips {
222 sec-alert {
223 temperature = <85000>;
224 hysteresis = <2000>;
225 type = "passive";
226 };
227
228 sec-crit {
229 temperature = <95000>;
230 hysteresis = <2000>;
231 type = "critical";
232 };
233 };
234 };
235 };
236
237 timer {
238 compatible = "arm,armv8-timer";
239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
240 IRQ_TYPE_LEVEL_LOW)>,
241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
242 IRQ_TYPE_LEVEL_LOW)>,
243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
244 IRQ_TYPE_LEVEL_LOW)>,
245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
246 IRQ_TYPE_LEVEL_LOW)>;
247 };
248
249 pmu {
250 compatible = "arm,cortex-a72-pmu";
251 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
255 interrupt-affinity = <&cpu0>,
256 <&cpu1>,
257 <&cpu2>,
258 <&cpu3>;
259 };
260
261 gic: interrupt-controller@1400000 {
262 compatible = "arm,gic-400";
263 #interrupt-cells = <3>;
264 interrupt-controller;
265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
266 <0x0 0x1420000 0 0x20000>, /* GICC */
267 <0x0 0x1440000 0 0x20000>, /* GICH */
268 <0x0 0x1460000 0 0x20000>; /* GICV */
269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
270 IRQ_TYPE_LEVEL_LOW)>;
271 };
272
273 soc: soc {
274 compatible = "simple-bus";
275 #address-cells = <2>;
276 #size-cells = <2>;
277 ranges;
278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
279 dma-coherent;
280
281 ddr: memory-controller@1080000 {
282 compatible = "fsl,qoriq-memory-controller";
283 reg = <0x0 0x1080000 0x0 0x1000>;
284 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
285 };
286
287 ifc: memory-controller@1530000 {
288 compatible = "fsl,ifc";
289 reg = <0x0 0x1530000 0x0 0x10000>;
290 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
291 status = "disabled";
292 };
293
294 qspi: spi@1550000 {
295 compatible = "fsl,ls1021a-qspi";
296 #address-cells = <1>;
297 #size-cells = <0>;
298 reg = <0x0 0x1550000 0x0 0x10000>,
299 <0x0 0x40000000 0x0 0x10000000>;
300 reg-names = "QuadSPI", "QuadSPI-memory";
301 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
302 clock-names = "qspi_en", "qspi";
303 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
304 QORIQ_CLK_PLL_DIV(2)>,
305 <&clockgen QORIQ_CLK_PLATFORM_PLL
306 QORIQ_CLK_PLL_DIV(2)>;
307 status = "disabled";
308 };
309
310 esdhc: mmc@1560000 {
311 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
312 reg = <0x0 0x1560000 0x0 0x10000>;
313 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
315 voltage-ranges = <1800 1800 3300 3300>;
316 sdhci,auto-cmd12;
317 bus-width = <4>;
318 };
319
320 scfg: scfg@1570000 {
321 compatible = "fsl,ls1046a-scfg", "syscon";
322 reg = <0x0 0x1570000 0x0 0x10000>;
323 big-endian;
324 #address-cells = <1>;
325 #size-cells = <1>;
326 ranges = <0x0 0x0 0x1570000 0x10000>;
327
328 extirq: interrupt-controller@1ac {
329 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
330 #interrupt-cells = <2>;
331 #address-cells = <0>;
332 interrupt-controller;
333 reg = <0x1ac 4>;
334 interrupt-map =
335 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
336 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
337 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
338 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
339 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
340 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
341 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
342 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
343 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
344 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
345 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
346 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-map-mask = <0xf 0x0>;
348 };
349 };
350
351 crypto: crypto@1700000 {
352 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
353 "fsl,sec-v4.0";
354 fsl,sec-era = <8>;
355 #address-cells = <1>;
356 #size-cells = <1>;
357 ranges = <0x0 0x00 0x1700000 0x100000>;
358 reg = <0x00 0x1700000 0x0 0x100000>;
359 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
360
361 sec_jr0: jr@10000 {
362 compatible = "fsl,sec-v5.4-job-ring",
363 "fsl,sec-v5.0-job-ring",
364 "fsl,sec-v4.0-job-ring";
365 reg = <0x10000 0x10000>;
366 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
367 };
368
369 sec_jr1: jr@20000 {
370 compatible = "fsl,sec-v5.4-job-ring",
371 "fsl,sec-v5.0-job-ring",
372 "fsl,sec-v4.0-job-ring";
373 reg = <0x20000 0x10000>;
374 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
375 };
376
377 sec_jr2: jr@30000 {
378 compatible = "fsl,sec-v5.4-job-ring",
379 "fsl,sec-v5.0-job-ring",
380 "fsl,sec-v4.0-job-ring";
381 reg = <0x30000 0x10000>;
382 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
383 };
384
385 sec_jr3: jr@40000 {
386 compatible = "fsl,sec-v5.4-job-ring",
387 "fsl,sec-v5.0-job-ring",
388 "fsl,sec-v4.0-job-ring";
389 reg = <0x40000 0x10000>;
390 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
391 };
392 };
393
394 qman: qman@1880000 {
395 compatible = "fsl,qman";
396 reg = <0x0 0x1880000 0x0 0x10000>;
397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
398 memory-region = <&qman_fqd &qman_pfdr>;
399
400 };
401
402 bman: bman@1890000 {
403 compatible = "fsl,bman";
404 reg = <0x0 0x1890000 0x0 0x10000>;
405 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
406 memory-region = <&bman_fbpr>;
407
408 };
409
410 qportals: qman-portals-bus@500000000 {
411 ranges = <0x0 0x5 0x00000000 0x8000000>;
412 };
413
414 bportals: bman-portals-bus@508000000 {
415 ranges = <0x0 0x5 0x08000000 0x8000000>;
416 };
417
418 sfp: efuse@1e80000 {
419 compatible = "fsl,ls1021a-sfp";
420 reg = <0x0 0x1e80000 0x0 0x10000>;
421 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
422 QORIQ_CLK_PLL_DIV(4)>;
423 clock-names = "sfp";
424 };
425
426 dcfg: dcfg@1ee0000 {
427 compatible = "fsl,ls1046a-dcfg", "syscon";
428 reg = <0x0 0x1ee0000 0x0 0x1000>;
429 big-endian;
430 };
431
432 clockgen: clocking@1ee1000 {
433 compatible = "fsl,ls1046a-clockgen";
434 reg = <0x0 0x1ee1000 0x0 0x1000>;
435 #clock-cells = <2>;
436 clocks = <&sysclk>;
437 };
438
439 tmu: tmu@1f00000 {
440 compatible = "fsl,qoriq-tmu";
441 reg = <0x0 0x1f00000 0x0 0x10000>;
442 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
443 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
444 fsl,tmu-calibration =
445 /* Calibration data group 1 */
446 <0x00000000 0x00000023>,
447 <0x00000001 0x00000029>,
448 <0x00000002 0x0000002f>,
449 <0x00000003 0x00000036>,
450 <0x00000004 0x0000003c>,
451 <0x00000005 0x00000042>,
452 <0x00000006 0x00000049>,
453 <0x00000007 0x0000004f>,
454 <0x00000008 0x00000055>,
455 <0x00000009 0x0000005c>,
456 <0x0000000a 0x00000062>,
457 <0x0000000b 0x00000068>,
458 /* Calibration data group 2 */
459 <0x00010000 0x00000022>,
460 <0x00010001 0x0000002a>,
461 <0x00010002 0x00000032>,
462 <0x00010003 0x0000003a>,
463 <0x00010004 0x00000042>,
464 <0x00010005 0x0000004a>,
465 <0x00010006 0x00000052>,
466 <0x00010007 0x0000005a>,
467 <0x00010008 0x00000062>,
468 <0x00010009 0x0000006a>,
469 /* Calibration data group 3 */
470 <0x00020000 0x00000021>,
471 <0x00020001 0x0000002b>,
472 <0x00020002 0x00000035>,
473 <0x00020003 0x0000003e>,
474 <0x00020004 0x00000048>,
475 <0x00020005 0x00000052>,
476 <0x00020006 0x0000005c>,
477 /* Calibration data group 4 */
478 <0x00030000 0x00000011>,
479 <0x00030001 0x0000001a>,
480 <0x00030002 0x00000024>,
481 <0x00030003 0x0000002e>,
482 <0x00030004 0x00000038>,
483 <0x00030005 0x00000042>,
484 <0x00030006 0x0000004c>,
485 <0x00030007 0x00000056>;
486 #thermal-sensor-cells = <1>;
487 };
488
489 dspi: spi@2100000 {
490 compatible = "fsl,ls1021a-v1.0-dspi";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <0x0 0x2100000 0x0 0x10000>;
494 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
495 clock-names = "dspi";
496 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
497 QORIQ_CLK_PLL_DIV(2)>;
498 spi-num-chipselects = <5>;
499 big-endian;
500 status = "disabled";
501 };
502
503 i2c0: i2c@2180000 {
504 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x0 0x2180000 0x0 0x10000>;
508 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
510 QORIQ_CLK_PLL_DIV(2)>;
511 dmas = <&edma0 1 38>,
512 <&edma0 1 39>;
513 dma-names = "rx", "tx";
514 status = "disabled";
515 };
516
517 i2c1: i2c@2190000 {
518 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 reg = <0x0 0x2190000 0x0 0x10000>;
522 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
524 QORIQ_CLK_PLL_DIV(2)>;
525 scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
526 status = "disabled";
527 };
528
529 i2c2: i2c@21a0000 {
530 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
531 #address-cells = <1>;
532 #size-cells = <0>;
533 reg = <0x0 0x21a0000 0x0 0x10000>;
534 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
536 QORIQ_CLK_PLL_DIV(2)>;
537 scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
538 status = "disabled";
539 };
540
541 i2c3: i2c@21b0000 {
542 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 reg = <0x0 0x21b0000 0x0 0x10000>;
546 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
548 QORIQ_CLK_PLL_DIV(2)>;
549 scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
550 status = "disabled";
551 };
552
553 duart0: serial@21c0500 {
554 compatible = "fsl,ns16550", "ns16550a";
555 reg = <0x00 0x21c0500 0x0 0x100>;
556 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
558 QORIQ_CLK_PLL_DIV(2)>;
559 status = "disabled";
560 };
561
562 duart1: serial@21c0600 {
563 compatible = "fsl,ns16550", "ns16550a";
564 reg = <0x00 0x21c0600 0x0 0x100>;
565 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
567 QORIQ_CLK_PLL_DIV(2)>;
568 status = "disabled";
569 };
570
571 duart2: serial@21d0500 {
572 compatible = "fsl,ns16550", "ns16550a";
573 reg = <0x0 0x21d0500 0x0 0x100>;
574 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
576 QORIQ_CLK_PLL_DIV(2)>;
577 status = "disabled";
578 };
579
580 duart3: serial@21d0600 {
581 compatible = "fsl,ns16550", "ns16550a";
582 reg = <0x0 0x21d0600 0x0 0x100>;
583 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
585 QORIQ_CLK_PLL_DIV(2)>;
586 status = "disabled";
587 };
588
589 gpio0: gpio@2300000 {
590 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
591 reg = <0x0 0x2300000 0x0 0x10000>;
592 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
597 };
598
599 gpio1: gpio@2310000 {
600 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
601 reg = <0x0 0x2310000 0x0 0x10000>;
602 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
603 gpio-controller;
604 #gpio-cells = <2>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 };
608
609 gpio2: gpio@2320000 {
610 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
611 reg = <0x0 0x2320000 0x0 0x10000>;
612 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
613 gpio-controller;
614 #gpio-cells = <2>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 };
618
619 gpio3: gpio@2330000 {
620 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
621 reg = <0x0 0x2330000 0x0 0x10000>;
622 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 gpio-controller;
624 #gpio-cells = <2>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
627 };
628
629 lpuart0: serial@2950000 {
630 compatible = "fsl,ls1021a-lpuart";
631 reg = <0x0 0x2950000 0x0 0x1000>;
632 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
634 QORIQ_CLK_PLL_DIV(1)>;
635 clock-names = "ipg";
636 status = "disabled";
637 };
638
639 lpuart1: serial@2960000 {
640 compatible = "fsl,ls1021a-lpuart";
641 reg = <0x0 0x2960000 0x0 0x1000>;
642 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
644 QORIQ_CLK_PLL_DIV(2)>;
645 clock-names = "ipg";
646 status = "disabled";
647 };
648
649 lpuart2: serial@2970000 {
650 compatible = "fsl,ls1021a-lpuart";
651 reg = <0x0 0x2970000 0x0 0x1000>;
652 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
654 QORIQ_CLK_PLL_DIV(2)>;
655 clock-names = "ipg";
656 status = "disabled";
657 };
658
659 lpuart3: serial@2980000 {
660 compatible = "fsl,ls1021a-lpuart";
661 reg = <0x0 0x2980000 0x0 0x1000>;
662 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
664 QORIQ_CLK_PLL_DIV(2)>;
665 clock-names = "ipg";
666 status = "disabled";
667 };
668
669 lpuart4: serial@2990000 {
670 compatible = "fsl,ls1021a-lpuart";
671 reg = <0x0 0x2990000 0x0 0x1000>;
672 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
674 QORIQ_CLK_PLL_DIV(2)>;
675 clock-names = "ipg";
676 status = "disabled";
677 };
678
679 lpuart5: serial@29a0000 {
680 compatible = "fsl,ls1021a-lpuart";
681 reg = <0x0 0x29a0000 0x0 0x1000>;
682 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
684 QORIQ_CLK_PLL_DIV(2)>;
685 clock-names = "ipg";
686 status = "disabled";
687 };
688
689 wdog0: watchdog@2ad0000 {
690 compatible = "fsl,imx21-wdt";
691 reg = <0x0 0x2ad0000 0x0 0x10000>;
692 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
694 QORIQ_CLK_PLL_DIV(2)>;
695 };
696
697 edma0: dma-controller@2c00000 {
698 #dma-cells = <2>;
699 compatible = "fsl,vf610-edma";
700 reg = <0x0 0x2c00000 0x0 0x10000>,
701 <0x0 0x2c10000 0x0 0x10000>,
702 <0x0 0x2c20000 0x0 0x10000>;
703 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-names = "edma-tx", "edma-err";
706 dma-channels = <32>;
707 big-endian;
708 clock-names = "dmamux0", "dmamux1";
709 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
710 QORIQ_CLK_PLL_DIV(2)>,
711 <&clockgen QORIQ_CLK_PLATFORM_PLL
712 QORIQ_CLK_PLL_DIV(2)>;
713 };
714
715 aux_bus: bus {
716 #address-cells = <2>;
717 #size-cells = <2>;
718 compatible = "simple-bus";
719 ranges;
720 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
721
722 usb0: usb@2f00000 {
723 compatible = "snps,dwc3";
724 reg = <0x0 0x2f00000 0x0 0x10000>;
725 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
726 dr_mode = "host";
727 snps,quirk-frame-length-adjustment = <0x20>;
728 snps,dis_rxdet_inp3_quirk;
729 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
730 usb3-lpm-capable;
731 };
732
733 usb1: usb@3000000 {
734 compatible = "snps,dwc3";
735 reg = <0x0 0x3000000 0x0 0x10000>;
736 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
737 dr_mode = "host";
738 snps,quirk-frame-length-adjustment = <0x20>;
739 snps,dis_rxdet_inp3_quirk;
740 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
741 usb3-lpm-capable;
742 };
743
744 usb2: usb@3100000 {
745 compatible = "snps,dwc3";
746 reg = <0x0 0x3100000 0x0 0x10000>;
747 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
748 dr_mode = "host";
749 snps,quirk-frame-length-adjustment = <0x20>;
750 snps,dis_rxdet_inp3_quirk;
751 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
752 usb3-lpm-capable;
753 };
754
755 sata: sata@3200000 {
756 compatible = "fsl,ls1046a-ahci";
757 reg = <0x0 0x3200000 0x0 0x10000>,
758 <0x0 0x20140520 0x0 0x4>;
759 reg-names = "ahci", "sata-ecc";
760 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
762 QORIQ_CLK_PLL_DIV(2)>;
763 };
764 };
765
766 msi1: msi-controller@1580000 {
767 compatible = "fsl,ls1046a-msi";
768 msi-controller;
769 reg = <0x0 0x1580000 0x0 0x10000>;
770 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
774 };
775
776 msi2: msi-controller@1590000 {
777 compatible = "fsl,ls1046a-msi";
778 msi-controller;
779 reg = <0x0 0x1590000 0x0 0x10000>;
780 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
784 };
785
786 msi3: msi-controller@15a0000 {
787 compatible = "fsl,ls1046a-msi";
788 msi-controller;
789 reg = <0x0 0x15a0000 0x0 0x10000>;
790 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
794 };
795
796 pcie1: pcie@3400000 {
797 compatible = "fsl,ls1046a-pcie";
798 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
799 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
800 reg-names = "regs", "config";
801 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
802 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
803 interrupt-names = "pme", "aer";
804 #address-cells = <3>;
805 #size-cells = <2>;
806 device_type = "pci";
807 num-viewport = <8>;
808 bus-range = <0x0 0xff>;
809 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
810 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
811 msi-parent = <&msi1>, <&msi2>, <&msi3>;
812 #interrupt-cells = <1>;
813 interrupt-map-mask = <0 0 0 7>;
814 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
815 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
816 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
817 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
818 big-endian;
819 status = "disabled";
820 };
821
822 pcie_ep1: pcie_ep@3400000 {
823 compatible = "fsl,ls1046a-pcie-ep";
824 reg = <0x00 0x03400000 0x0 0x00100000>,
825 <0x40 0x00000000 0x8 0x00000000>;
826 reg-names = "regs", "addr_space";
827 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
828 interrupt-names = "pme";
829 num-ib-windows = <6>;
830 num-ob-windows = <8>;
831 big-endian;
832 status = "disabled";
833 };
834
835 pcie2: pcie@3500000 {
836 compatible = "fsl,ls1046a-pcie";
837 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
838 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
839 reg-names = "regs", "config";
840 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
841 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
842 interrupt-names = "pme", "aer";
843 #address-cells = <3>;
844 #size-cells = <2>;
845 device_type = "pci";
846 num-viewport = <8>;
847 bus-range = <0x0 0xff>;
848 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
849 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
850 msi-parent = <&msi2>, <&msi3>, <&msi1>;
851 #interrupt-cells = <1>;
852 interrupt-map-mask = <0 0 0 7>;
853 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
854 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
855 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
857 big-endian;
858 status = "disabled";
859 };
860
861 pcie_ep2: pcie_ep@3500000 {
862 compatible = "fsl,ls1046a-pcie-ep";
863 reg = <0x00 0x03500000 0x0 0x00100000>,
864 <0x48 0x00000000 0x8 0x00000000>;
865 reg-names = "regs", "addr_space";
866 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
867 interrupt-names = "pme";
868 num-ib-windows = <6>;
869 num-ob-windows = <8>;
870 big-endian;
871 status = "disabled";
872 };
873
874 pcie3: pcie@3600000 {
875 compatible = "fsl,ls1046a-pcie";
876 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
877 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
878 reg-names = "regs", "config";
879 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
880 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
881 interrupt-names = "pme", "aer";
882 #address-cells = <3>;
883 #size-cells = <2>;
884 device_type = "pci";
885 num-viewport = <8>;
886 bus-range = <0x0 0xff>;
887 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
888 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
889 msi-parent = <&msi3>, <&msi1>, <&msi2>;
890 #interrupt-cells = <1>;
891 interrupt-map-mask = <0 0 0 7>;
892 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
893 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
894 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
895 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
896 big-endian;
897 status = "disabled";
898 };
899
900 pcie_ep3: pcie_ep@3600000 {
901 compatible = "fsl,ls1046a-pcie-ep";
902 reg = <0x00 0x03600000 0x0 0x00100000>,
903 <0x50 0x00000000 0x8 0x00000000>;
904 reg-names = "regs", "addr_space";
905 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
906 interrupt-names = "pme";
907 num-ib-windows = <6>;
908 num-ob-windows = <8>;
909 big-endian;
910 status = "disabled";
911 };
912
913 qdma: dma-controller@8380000 {
914 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
915 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
916 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
917 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
918 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "qdma-error", "qdma-queue0",
924 "qdma-queue1", "qdma-queue2", "qdma-queue3";
925 #dma-cells = <1>;
926 dma-channels = <8>;
927 block-number = <1>;
928 block-offset = <0x10000>;
929 fsl,dma-queues = <2>;
930 status-sizes = <64>;
931 queue-sizes = <64 64>;
932 big-endian;
933 };
934
935 rcpm: wakeup-controller@1ee2140 {
936 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
937 reg = <0x0 0x1ee2140 0x0 0x4>;
938 #fsl,rcpm-wakeup-cells = <1>;
939 };
940
941 ftm_alarm0: rtc@29d0000 {
942 compatible = "fsl,ls1046a-ftm-alarm";
943 reg = <0x0 0x29d0000 0x0 0x10000>;
944 fsl,rcpm-wakeup = <&rcpm 0x20000>;
945 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
946 big-endian;
947 };
948 };
949
950 reserved-memory {
951 #address-cells = <2>;
952 #size-cells = <2>;
953 ranges;
954
955 bman_fbpr: bman-fbpr {
956 compatible = "shared-dma-pool";
957 size = <0 0x1000000>;
958 alignment = <0 0x1000000>;
959 no-map;
960 };
961
962 qman_fqd: qman-fqd {
963 compatible = "shared-dma-pool";
964 size = <0 0x800000>;
965 alignment = <0 0x800000>;
966 no-map;
967 };
968
969 qman_pfdr: qman-pfdr {
970 compatible = "shared-dma-pool";
971 size = <0 0x2000000>;
972 alignment = <0 0x2000000>;
973 no-map;
974 };
975 };
976
977 firmware {
978 optee {
979 compatible = "linaro,optee-tz";
980 method = "smc";
981 };
982 };
983 };
984
985 #include "qoriq-qman-portals.dtsi"
986 #include "qoriq-bman-portals.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.