1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
16 };
17
18 dma_subsys: bus@5a000000 {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
23
24 lpspi0: spi@5a000000 {
25 compatible = "fsl,imx7ulp-spi";
26 reg = <0x5a000000 0x10000>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
30 interrupt-parent = <&gic>;
31 clocks = <&spi0_lpcg IMX_LPCG_CLK_0>,
32 <&spi0_lpcg IMX_LPCG_CLK_4>;
33 clock-names = "per", "ipg";
34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
36 power-domains = <&pd IMX_SC_R_SPI_0>;
37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>;
38 dma-names = "tx", "rx";
39 status = "disabled";
40 };
41
42 lpspi1: spi@5a010000 {
43 compatible = "fsl,imx7ulp-spi";
44 reg = <0x5a010000 0x10000>;
45 #address-cells = <1>;
46 #size-cells = <0>;
47 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-parent = <&gic>;
49 clocks = <&spi1_lpcg IMX_LPCG_CLK_0>,
50 <&spi1_lpcg IMX_LPCG_CLK_4>;
51 clock-names = "per", "ipg";
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
54 power-domains = <&pd IMX_SC_R_SPI_1>;
55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>;
56 dma-names = "tx", "rx";
57 status = "disabled";
58 };
59
60 lpspi2: spi@5a020000 {
61 compatible = "fsl,imx7ulp-spi";
62 reg = <0x5a020000 0x10000>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
66 interrupt-parent = <&gic>;
67 clocks = <&spi2_lpcg IMX_LPCG_CLK_0>,
68 <&spi2_lpcg IMX_LPCG_CLK_4>;
69 clock-names = "per", "ipg";
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
72 power-domains = <&pd IMX_SC_R_SPI_2>;
73 dmas = <&edma2 5 0 0>, <&edma2 4 0 FSL_EDMA_RX>;
74 dma-names = "tx", "rx";
75 status = "disabled";
76 };
77
78 lpspi3: spi@5a030000 {
79 compatible = "fsl,imx7ulp-spi";
80 reg = <0x5a030000 0x10000>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-parent = <&gic>;
85 clocks = <&spi3_lpcg IMX_LPCG_CLK_0>,
86 <&spi3_lpcg IMX_LPCG_CLK_4>;
87 clock-names = "per", "ipg";
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
90 power-domains = <&pd IMX_SC_R_SPI_3>;
91 dmas = <&edma2 7 0 0>, <&edma2 6 0 FSL_EDMA_RX>;
92 dma-names = "tx", "rx";
93 status = "disabled";
94 };
95
96 lpuart0: serial@5a060000 {
97 reg = <0x5a060000 0x1000>;
98 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
100 <&uart0_lpcg IMX_LPCG_CLK_0>;
101 clock-names = "ipg", "baud";
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned-clock-rates = <80000000>;
104 power-domains = <&pd IMX_SC_R_UART_0>;
105 dma-names = "rx", "tx";
106 dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>;
107 status = "disabled";
108 };
109
110 lpuart1: serial@5a070000 {
111 reg = <0x5a070000 0x1000>;
112 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
114 <&uart1_lpcg IMX_LPCG_CLK_0>;
115 clock-names = "ipg", "baud";
116 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
117 assigned-clock-rates = <80000000>;
118 power-domains = <&pd IMX_SC_R_UART_1>;
119 dma-names = "rx", "tx";
120 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>;
121 status = "disabled";
122 };
123
124 lpuart2: serial@5a080000 {
125 reg = <0x5a080000 0x1000>;
126 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
128 <&uart2_lpcg IMX_LPCG_CLK_0>;
129 clock-names = "ipg", "baud";
130 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
131 assigned-clock-rates = <80000000>;
132 power-domains = <&pd IMX_SC_R_UART_2>;
133 dma-names = "rx", "tx";
134 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
135 status = "disabled";
136 };
137
138 lpuart3: serial@5a090000 {
139 reg = <0x5a090000 0x1000>;
140 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
142 <&uart3_lpcg IMX_LPCG_CLK_0>;
143 clock-names = "ipg", "baud";
144 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
145 assigned-clock-rates = <80000000>;
146 power-domains = <&pd IMX_SC_R_UART_3>;
147 dma-names = "rx", "tx";
148 dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
149 status = "disabled";
150 };
151
152 adma_pwm: pwm@5a190000 {
153 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
154 reg = <0x5a190000 0x1000>;
155 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>,
157 <&adma_pwm_lpcg IMX_LPCG_CLK_0>;
158 clock-names = "ipg", "per";
159 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
160 assigned-clock-rates = <24000000>;
161 #pwm-cells = <3>;
162 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
163 };
164
165 edma2: dma-controller@5a1f0000 {
166 compatible = "fsl,imx8qm-edma";
167 reg = <0x5a1f0000 0x170000>;
168 #dma-cells = <3>;
169 dma-channels = <16>;
170 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
186 power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
187 <&pd IMX_SC_R_DMA_2_CH1>,
188 <&pd IMX_SC_R_DMA_2_CH2>,
189 <&pd IMX_SC_R_DMA_2_CH3>,
190 <&pd IMX_SC_R_DMA_2_CH4>,
191 <&pd IMX_SC_R_DMA_2_CH5>,
192 <&pd IMX_SC_R_DMA_2_CH6>,
193 <&pd IMX_SC_R_DMA_2_CH7>,
194 <&pd IMX_SC_R_DMA_2_CH8>,
195 <&pd IMX_SC_R_DMA_2_CH9>,
196 <&pd IMX_SC_R_DMA_2_CH10>,
197 <&pd IMX_SC_R_DMA_2_CH11>,
198 <&pd IMX_SC_R_DMA_2_CH12>,
199 <&pd IMX_SC_R_DMA_2_CH13>,
200 <&pd IMX_SC_R_DMA_2_CH14>,
201 <&pd IMX_SC_R_DMA_2_CH15>;
202 };
203
204 spi0_lpcg: clock-controller@5a400000 {
205 compatible = "fsl,imx8qxp-lpcg";
206 reg = <0x5a400000 0x10000>;
207 #clock-cells = <1>;
208 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
209 <&dma_ipg_clk>;
210 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
211 clock-output-names = "spi0_lpcg_clk",
212 "spi0_lpcg_ipg_clk";
213 power-domains = <&pd IMX_SC_R_SPI_0>;
214 };
215
216 spi1_lpcg: clock-controller@5a410000 {
217 compatible = "fsl,imx8qxp-lpcg";
218 reg = <0x5a410000 0x10000>;
219 #clock-cells = <1>;
220 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
221 <&dma_ipg_clk>;
222 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
223 clock-output-names = "spi1_lpcg_clk",
224 "spi1_lpcg_ipg_clk";
225 power-domains = <&pd IMX_SC_R_SPI_1>;
226 };
227
228 spi2_lpcg: clock-controller@5a420000 {
229 compatible = "fsl,imx8qxp-lpcg";
230 reg = <0x5a420000 0x10000>;
231 #clock-cells = <1>;
232 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
233 <&dma_ipg_clk>;
234 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
235 clock-output-names = "spi2_lpcg_clk",
236 "spi2_lpcg_ipg_clk";
237 power-domains = <&pd IMX_SC_R_SPI_2>;
238 };
239
240 spi3_lpcg: clock-controller@5a430000 {
241 compatible = "fsl,imx8qxp-lpcg";
242 reg = <0x5a430000 0x10000>;
243 #clock-cells = <1>;
244 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
245 <&dma_ipg_clk>;
246 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
247 clock-output-names = "spi3_lpcg_clk",
248 "spi3_lpcg_ipg_clk";
249 power-domains = <&pd IMX_SC_R_SPI_3>;
250 };
251
252 uart0_lpcg: clock-controller@5a460000 {
253 compatible = "fsl,imx8qxp-lpcg";
254 reg = <0x5a460000 0x10000>;
255 #clock-cells = <1>;
256 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
257 <&dma_ipg_clk>;
258 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
259 clock-output-names = "uart0_lpcg_baud_clk",
260 "uart0_lpcg_ipg_clk";
261 power-domains = <&pd IMX_SC_R_UART_0>;
262 };
263
264 uart1_lpcg: clock-controller@5a470000 {
265 compatible = "fsl,imx8qxp-lpcg";
266 reg = <0x5a470000 0x10000>;
267 #clock-cells = <1>;
268 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
269 <&dma_ipg_clk>;
270 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
271 clock-output-names = "uart1_lpcg_baud_clk",
272 "uart1_lpcg_ipg_clk";
273 power-domains = <&pd IMX_SC_R_UART_1>;
274 };
275
276 uart2_lpcg: clock-controller@5a480000 {
277 compatible = "fsl,imx8qxp-lpcg";
278 reg = <0x5a480000 0x10000>;
279 #clock-cells = <1>;
280 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
281 <&dma_ipg_clk>;
282 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
283 clock-output-names = "uart2_lpcg_baud_clk",
284 "uart2_lpcg_ipg_clk";
285 power-domains = <&pd IMX_SC_R_UART_2>;
286 };
287
288 uart3_lpcg: clock-controller@5a490000 {
289 compatible = "fsl,imx8qxp-lpcg";
290 reg = <0x5a490000 0x10000>;
291 #clock-cells = <1>;
292 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
293 <&dma_ipg_clk>;
294 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
295 clock-output-names = "uart3_lpcg_baud_clk",
296 "uart3_lpcg_ipg_clk";
297 power-domains = <&pd IMX_SC_R_UART_3>;
298 };
299
300 adma_pwm_lpcg: clock-controller@5a590000 {
301 compatible = "fsl,imx8qxp-lpcg";
302 reg = <0x5a590000 0x10000>;
303 #clock-cells = <1>;
304 clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
305 <&dma_ipg_clk>;
306 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
307 clock-output-names = "adma_pwm_lpcg_clk",
308 "adma_pwm_lpcg_ipg_clk";
309 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
310 };
311
312 i2c0: i2c@5a800000 {
313 reg = <0x5a800000 0x4000>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>,
318 <&i2c0_lpcg IMX_LPCG_CLK_4>;
319 clock-names = "per", "ipg";
320 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
321 assigned-clock-rates = <24000000>;
322 power-domains = <&pd IMX_SC_R_I2C_0>;
323 status = "disabled";
324 };
325
326 i2c1: i2c@5a810000 {
327 reg = <0x5a810000 0x4000>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>,
332 <&i2c1_lpcg IMX_LPCG_CLK_4>;
333 clock-names = "per", "ipg";
334 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
335 assigned-clock-rates = <24000000>;
336 power-domains = <&pd IMX_SC_R_I2C_1>;
337 status = "disabled";
338 };
339
340 i2c2: i2c@5a820000 {
341 reg = <0x5a820000 0x4000>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>,
346 <&i2c2_lpcg IMX_LPCG_CLK_4>;
347 clock-names = "per", "ipg";
348 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
349 assigned-clock-rates = <24000000>;
350 power-domains = <&pd IMX_SC_R_I2C_2>;
351 status = "disabled";
352 };
353
354 i2c3: i2c@5a830000 {
355 reg = <0x5a830000 0x4000>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>,
360 <&i2c3_lpcg IMX_LPCG_CLK_4>;
361 clock-names = "per", "ipg";
362 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
363 assigned-clock-rates = <24000000>;
364 power-domains = <&pd IMX_SC_R_I2C_3>;
365 status = "disabled";
366 };
367
368 adc0: adc@5a880000 {
369 compatible = "nxp,imx8qxp-adc";
370 #io-channel-cells = <1>;
371 reg = <0x5a880000 0x10000>;
372 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-parent = <&gic>;
374 clocks = <&adc0_lpcg IMX_LPCG_CLK_0>,
375 <&adc0_lpcg IMX_LPCG_CLK_4>;
376 clock-names = "per", "ipg";
377 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
378 assigned-clock-rates = <24000000>;
379 power-domains = <&pd IMX_SC_R_ADC_0>;
380 status = "disabled";
381 };
382
383 adc1: adc@5a890000 {
384 compatible = "nxp,imx8qxp-adc";
385 #io-channel-cells = <1>;
386 reg = <0x5a890000 0x10000>;
387 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
388 interrupt-parent = <&gic>;
389 clocks = <&adc1_lpcg IMX_LPCG_CLK_0>,
390 <&adc1_lpcg IMX_LPCG_CLK_4>;
391 clock-names = "per", "ipg";
392 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
393 assigned-clock-rates = <24000000>;
394 power-domains = <&pd IMX_SC_R_ADC_1>;
395 status = "disabled";
396 };
397
398 flexcan1: can@5a8d0000 {
399 compatible = "fsl,imx8qm-flexcan";
400 reg = <0x5a8d0000 0x10000>;
401 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-parent = <&gic>;
403 clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
404 <&can0_lpcg IMX_LPCG_CLK_0>;
405 clock-names = "ipg", "per";
406 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
407 assigned-clock-rates = <40000000>;
408 power-domains = <&pd IMX_SC_R_CAN_0>;
409 /* SLSlice[4] */
410 fsl,clk-source = /bits/ 8 <0>;
411 fsl,scu-index = /bits/ 8 <0>;
412 status = "disabled";
413 };
414
415 flexcan2: can@5a8e0000 {
416 compatible = "fsl,imx8qm-flexcan";
417 reg = <0x5a8e0000 0x10000>;
418 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
419 interrupt-parent = <&gic>;
420 /* CAN0 clock and PD is shared among all CAN instances as
421 * CAN1 shares CAN0's clock and to enable CAN0's clock it
422 * has to be powered on.
423 */
424 clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
425 <&can0_lpcg IMX_LPCG_CLK_0>;
426 clock-names = "ipg", "per";
427 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
428 assigned-clock-rates = <40000000>;
429 power-domains = <&pd IMX_SC_R_CAN_1>;
430 /* SLSlice[4] */
431 fsl,clk-source = /bits/ 8 <0>;
432 fsl,scu-index = /bits/ 8 <1>;
433 status = "disabled";
434 };
435
436 flexcan3: can@5a8f0000 {
437 compatible = "fsl,imx8qm-flexcan";
438 reg = <0x5a8f0000 0x10000>;
439 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-parent = <&gic>;
441 /* CAN0 clock and PD is shared among all CAN instances as
442 * CAN2 shares CAN0's clock and to enable CAN0's clock it
443 * has to be powered on.
444 */
445 clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
446 <&can0_lpcg IMX_LPCG_CLK_0>;
447 clock-names = "ipg", "per";
448 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
449 assigned-clock-rates = <40000000>;
450 power-domains = <&pd IMX_SC_R_CAN_2>;
451 /* SLSlice[4] */
452 fsl,clk-source = /bits/ 8 <0>;
453 fsl,scu-index = /bits/ 8 <2>;
454 status = "disabled";
455 };
456
457 edma3: dma-controller@5a9f0000 {
458 compatible = "fsl,imx8qm-edma";
459 reg = <0x5a9f0000 0x90000>;
460 #dma-cells = <3>;
461 dma-channels = <8>;
462 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
470 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
471 <&pd IMX_SC_R_DMA_3_CH1>,
472 <&pd IMX_SC_R_DMA_3_CH2>,
473 <&pd IMX_SC_R_DMA_3_CH3>,
474 <&pd IMX_SC_R_DMA_3_CH4>,
475 <&pd IMX_SC_R_DMA_3_CH5>,
476 <&pd IMX_SC_R_DMA_3_CH6>,
477 <&pd IMX_SC_R_DMA_3_CH7>;
478 };
479
480 i2c0_lpcg: clock-controller@5ac00000 {
481 compatible = "fsl,imx8qxp-lpcg";
482 reg = <0x5ac00000 0x10000>;
483 #clock-cells = <1>;
484 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
485 <&dma_ipg_clk>;
486 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
487 clock-output-names = "i2c0_lpcg_clk",
488 "i2c0_lpcg_ipg_clk";
489 power-domains = <&pd IMX_SC_R_I2C_0>;
490 };
491
492 i2c1_lpcg: clock-controller@5ac10000 {
493 compatible = "fsl,imx8qxp-lpcg";
494 reg = <0x5ac10000 0x10000>;
495 #clock-cells = <1>;
496 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
497 <&dma_ipg_clk>;
498 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
499 clock-output-names = "i2c1_lpcg_clk",
500 "i2c1_lpcg_ipg_clk";
501 power-domains = <&pd IMX_SC_R_I2C_1>;
502 };
503
504 i2c2_lpcg: clock-controller@5ac20000 {
505 compatible = "fsl,imx8qxp-lpcg";
506 reg = <0x5ac20000 0x10000>;
507 #clock-cells = <1>;
508 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
509 <&dma_ipg_clk>;
510 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
511 clock-output-names = "i2c2_lpcg_clk",
512 "i2c2_lpcg_ipg_clk";
513 power-domains = <&pd IMX_SC_R_I2C_2>;
514 };
515
516 i2c3_lpcg: clock-controller@5ac30000 {
517 compatible = "fsl,imx8qxp-lpcg";
518 reg = <0x5ac30000 0x10000>;
519 #clock-cells = <1>;
520 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
521 <&dma_ipg_clk>;
522 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
523 clock-output-names = "i2c3_lpcg_clk",
524 "i2c3_lpcg_ipg_clk";
525 power-domains = <&pd IMX_SC_R_I2C_3>;
526 };
527
528 adc0_lpcg: clock-controller@5ac80000 {
529 compatible = "fsl,imx8qxp-lpcg";
530 reg = <0x5ac80000 0x10000>;
531 #clock-cells = <1>;
532 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
533 <&dma_ipg_clk>;
534 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
535 clock-output-names = "adc0_lpcg_clk",
536 "adc0_lpcg_ipg_clk";
537 power-domains = <&pd IMX_SC_R_ADC_0>;
538 };
539
540 adc1_lpcg: clock-controller@5ac90000 {
541 compatible = "fsl,imx8qxp-lpcg";
542 reg = <0x5ac90000 0x10000>;
543 #clock-cells = <1>;
544 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
545 <&dma_ipg_clk>;
546 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
547 clock-output-names = "adc1_lpcg_clk",
548 "adc1_lpcg_ipg_clk";
549 power-domains = <&pd IMX_SC_R_ADC_1>;
550 };
551
552 can0_lpcg: clock-controller@5acd0000 {
553 compatible = "fsl,imx8qxp-lpcg";
554 reg = <0x5acd0000 0x10000>;
555 #clock-cells = <1>;
556 clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
557 <&dma_ipg_clk>, <&dma_ipg_clk>;
558 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
559 clock-output-names = "can0_lpcg_pe_clk",
560 "can0_lpcg_ipg_clk",
561 "can0_lpcg_chi_clk";
562 power-domains = <&pd IMX_SC_R_CAN_0>;
563 };
564 };
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