1 // SPDX-License-Identifier: GPL-2.0-only and MIT
2
3 /*
4 * Copyright 2024 NXP
5 */
6
7 mipi0_subsys: bus@56220000 {
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi0>;
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x56220000 0x0 0x56220000 0x10000>;
13
14 irqsteer_mipi0: interrupt-controller@56220000 {
15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
16 reg = <0x56220000 0x1000>;
17 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
21 clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_MIPI_0>;
24 fsl,channel = <0>;
25 fsl,num-irqs = <32>;
26 };
27
28 mipi0_lis_lpcg: clock-controller@56223000 {
29 compatible = "fsl,imx8qxp-lpcg";
30 reg = <0x56223000 0x4>;
31 #clock-cells = <1>;
32 power-domains = <&pd IMX_SC_R_MIPI_0>;
33 };
34
35 mipi0_pwm_lpcg: clock-controller@5622300c {
36 compatible = "fsl,imx8qxp-lpcg";
37 reg = <0x5622300c 0x4>;
38 #clock-cells = <1>;
39 power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
40 };
41
42 mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
43 compatible = "fsl,imx8qxp-lpcg";
44 reg = <0x56223014 0x4>;
45 #clock-cells = <1>;
46 clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
47 clock-indices = <IMX_LPCG_CLK_0>;
48 clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
49 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
50 };
51
52 mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
53 compatible = "fsl,imx8qxp-lpcg";
54 reg = <0x56223018 0x4>;
55 #clock-cells = <1>;
56 clocks = <&dsi_ipg_clk>;
57 clock-indices = <IMX_LPCG_CLK_0>;
58 clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
59 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
60 };
61
62 mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
63 compatible = "fsl,imx8qxp-lpcg";
64 reg = <0x5622301c 0x4>;
65 #clock-cells = <1>;
66 clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
67 clock-indices = <IMX_LPCG_CLK_0>;
68 clock-output-names = "mipi0_i2c0_lpcg_clk";
69 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
70 };
71
72 mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
73 compatible = "fsl,imx8qxp-lpcg";
74 reg = <0x56223024 0x4>;
75 #clock-cells = <1>;
76 clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
77 clock-indices = <IMX_LPCG_CLK_0>;
78 clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
79 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
80 };
81
82 mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
83 compatible = "fsl,imx8qxp-lpcg";
84 reg = <0x56223028 0x4>;
85 #clock-cells = <1>;
86 clocks = <&dsi_ipg_clk>;
87 clock-indices = <IMX_LPCG_CLK_0>;
88 clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
89 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
90 };
91
92 mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
93 compatible = "fsl,imx8qxp-lpcg";
94 reg = <0x5622302c 0x4>;
95 #clock-cells = <1>;
96 clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
97 clock-indices = <IMX_LPCG_CLK_0>;
98 clock-output-names = "mipi0_i2c1_lpcg_clk";
99 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
100 };
101
102 pwm_mipi0: pwm@56224000 {
103 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
104 reg = <0x56224000 0x1000>;
105 clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
106 <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
107 clock-names = "ipg", "per";
108 assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
109 assigned-clock-rates = <24000000>;
110 #pwm-cells = <3>;
111 power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
112 status = "disabled";
113 };
114
115 i2c0_mipi0: i2c@56226000 {
116 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
117 reg = <0x56226000 0x1000>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 interrupts = <8>;
121 clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
122 <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
123 clock-names = "per", "ipg";
124 assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
125 assigned-clock-rates = <24000000>;
126 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
127 status = "disabled";
128 };
129 };
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