1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7
8 / {
9
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
14 };
15
16 leds {
17 compatible = "gpio-leds";
18
19 led0 {
20 label = "gen_led0";
21 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
22 default-state = "off";
23 };
24
25 led1 {
26 label = "gen_led1";
27 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
28 default-state = "off";
29 };
30
31 led2 {
32 label = "gen_led2";
33 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
35 };
36
37 led3 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_led3>;
40 label = "heartbeat";
41 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
42 linux,default-trigger = "heartbeat";
43 };
44 };
45
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <100000000>;
50 };
51
52 pcie0_refclk_gated: pcie0-refclk-gated {
53 compatible = "gpio-gate-clock";
54 clocks = <&pcie0_refclk>;
55 #clock-cells = <0>;
56 enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
57 };
58
59 reg_1v5: regulator-1v5 {
60 compatible = "regulator-fixed";
61 regulator-name = "1V5";
62 regulator-min-microvolt = <1500000>;
63 regulator-max-microvolt = <1500000>;
64 };
65
66 reg_1v8: regulator-1v8 {
67 compatible = "regulator-fixed";
68 regulator-name = "1V8";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <1800000>;
71 };
72
73 reg_audio: regulator-audio {
74 compatible = "regulator-fixed";
75 regulator-name = "3v3_aud";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
79 enable-active-high;
80 };
81
82 reg_usbotg1: regulator-usbotg1 {
83 compatible = "regulator-fixed";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_reg_usb_otg1>;
86 regulator-name = "usb_otg_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_camera: regulator-camera {
94 compatible = "regulator-fixed";
95 regulator-name = "mipi_pwr";
96 regulator-min-microvolt = <2800000>;
97 regulator-max-microvolt = <2800000>;
98 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
99 enable-active-high;
100 startup-delay-us = <100000>;
101 };
102
103 reg_pcie0: regulator-pcie {
104 compatible = "regulator-fixed";
105 regulator-name = "pci_pwr_en";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 enable-active-high;
109 gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
110 startup-delay-us = <100000>;
111 };
112
113 reg_usdhc2_vmmc: regulator-usdhc2 {
114 compatible = "regulator-fixed";
115 regulator-name = "VSD_3V3";
116 regulator-min-microvolt = <3300000>;
117 regulator-max-microvolt = <3300000>;
118 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
119 enable-active-high;
120 };
121
122 sound-dmic {
123 compatible = "simple-audio-card";
124 simple-audio-card,name = "dmic";
125 simple-audio-card,format = "pdm";
126 simple-audio-card,bitclock-master = <&dailink_master>;
127 simple-audio-card,frame-master = <&dailink_master>;
128
129 dailink_master: simple-audio-card,cpu {
130 sound-dai = <&micfil>;
131 };
132
133 simple-audio-card,codec {
134 sound-dai = <&dmic_codec>;
135 };
136 };
137
138 sound-wm8962 {
139 compatible = "simple-audio-card";
140 simple-audio-card,name = "wm8962";
141 simple-audio-card,format = "i2s";
142 simple-audio-card,widgets = "Headphone", "Headphones",
143 "Microphone", "Headset Mic",
144 "Speaker", "Speaker";
145 simple-audio-card,routing = "Headphones", "HPOUTL",
146 "Headphones", "HPOUTR",
147 "Speaker", "SPKOUTL",
148 "Speaker", "SPKOUTR",
149 "Headset Mic", "MICBIAS",
150 "IN3R", "Headset Mic";
151
152 simple-audio-card,cpu {
153 sound-dai = <&sai3>;
154 };
155
156 simple-audio-card,codec {
157 sound-dai = <&wm8962>;
158 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
159 frame-master;
160 bitclock-master;
161 };
162 };
163 };
164
165 &csi {
166 status = "okay";
167 };
168
169 &ecspi2 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_espi2>;
172 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
173 status = "okay";
174
175 eeprom@0 {
176 compatible = "microchip,at25160bn", "atmel,at25";
177 reg = <0>;
178 spi-max-frequency = <5000000>;
179 spi-cpha;
180 spi-cpol;
181 pagesize = <32>;
182 size = <2048>;
183 address-width = <16>;
184 };
185 };
186
187 &i2c2 {
188 clock-frequency = <400000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c2>;
191 status = "okay";
192
193 camera@10 {
194 compatible = "ovti,ov5640";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_ov5640>;
197 reg = <0x10>;
198 clocks = <&clk IMX8MM_CLK_CLKO1>;
199 clock-names = "xclk";
200 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
201 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
202 assigned-clock-rates = <24000000>;
203 AVDD-supply = <®_camera>; /* 2.8v */
204 DVDD-supply = <®_1v5>;
205 DOVDD-supply = <®_1v8>;
206 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
207 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
208
209 port {
210 /* MIPI CSI-2 bus endpoint */
211 ov5640_to_mipi_csi2: endpoint {
212 remote-endpoint = <&imx8mm_mipi_csi_in>;
213 clock-lanes = <0>;
214 data-lanes = <1 2>;
215 };
216 };
217 };
218 };
219
220 &i2c4 {
221 clock-frequency = <400000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c4>;
224 status = "okay";
225
226 wm8962: audio-codec@1a {
227 compatible = "wlf,wm8962";
228 reg = <0x1a>;
229 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
230 DCVDD-supply = <®_audio>;
231 DBVDD-supply = <®_audio>;
232 AVDD-supply = <®_audio>;
233 CPVDD-supply = <®_audio>;
234 MICVDD-supply = <®_audio>;
235 PLLVDD-supply = <®_audio>;
236 SPKVDD1-supply = <®_audio>;
237 SPKVDD2-supply = <®_audio>;
238 gpio-cfg = <
239 0x0000 /* 0:Default */
240 0x0000 /* 1:Default */
241 0x0000 /* 2:FN_DMICCLK */
242 0x0000 /* 3:Default */
243 0x0000 /* 4:FN_DMICCDAT */
244 0x0000 /* 5:Default */
245 >;
246 #sound-dai-cells = <0>;
247 };
248
249 pca6416_0: gpio@20 {
250 compatible = "nxp,pcal6416";
251 reg = <0x20>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_pcal6414>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-parent = <&gpio4>;
257 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
258 };
259
260 pca6416_1: gpio@21 {
261 compatible = "nxp,pcal6416";
262 reg = <0x21>;
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-parent = <&gpio4>;
266 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
267 };
268 };
269
270 &micfil {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_pdm>;
273 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
274 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
275 assigned-clock-rates = <49152000>;
276 status = "okay";
277 };
278
279 &mipi_csi {
280 status = "okay";
281 ports {
282 port@0 {
283 imx8mm_mipi_csi_in: endpoint {
284 remote-endpoint = <&ov5640_to_mipi_csi2>;
285 data-lanes = <1 2>;
286 };
287 };
288 };
289 };
290
291 &pcie_phy {
292 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
293 fsl,tx-deemph-gen1 = <0x2d>;
294 fsl,tx-deemph-gen2 = <0xf>;
295 fsl,clkreq-unsupported;
296 clocks = <&pcie0_refclk_gated>;
297 clock-names = "ref";
298 status = "okay";
299 };
300
301 &pcie0 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_pcie0>;
304 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
305 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
306 <&clk IMX8MM_CLK_PCIE1_AUX>;
307 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
308 <&clk IMX8MM_CLK_PCIE1_CTRL>;
309 assigned-clock-rates = <10000000>, <250000000>;
310 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
311 <&clk IMX8MM_SYS_PLL2_250M>;
312 vpcie-supply = <®_pcie0>;
313 status = "okay";
314 };
315
316 &sai3 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_sai3>;
319 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
320 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
321 assigned-clock-rates = <24576000>;
322 fsl,sai-mclk-direction-output;
323 status = "okay";
324 };
325
326 &snvs_pwrkey {
327 status = "okay";
328 };
329
330 &uart2 { /* console */
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_uart2>;
333 status = "okay";
334 };
335
336 &uart3 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_uart3>;
339 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
340 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
341 uart-has-rtscts;
342 status = "okay";
343 };
344
345 &usbotg1 {
346 vbus-supply = <®_usbotg1>;
347 disable-over-current;
348 dr_mode = "otg";
349 status = "okay";
350 };
351
352 &usbotg2 {
353 disable-over-current;
354 dr_mode = "host";
355 status = "okay";
356 };
357
358 &usbphynop2 {
359 reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
360 };
361
362 &usdhc2 {
363 pinctrl-names = "default", "state_100mhz", "state_200mhz";
364 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
365 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
366 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
367 bus-width = <4>;
368 vmmc-supply = <®_usdhc2_vmmc>;
369 status = "okay";
370 };
371
372 &iomuxc {
373 pinctrl_espi2: espi2grp {
374 fsl,pins = <
375 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
376 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
377 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
378 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
379 >;
380 };
381
382 pinctrl_i2c2: i2c2grp {
383 fsl,pins = <
384 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
385 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
386 >;
387 };
388
389 pinctrl_i2c4: i2c4grp {
390 fsl,pins = <
391 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
392 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
393 >;
394 };
395
396 pinctrl_led3: led3grp {
397 fsl,pins = <
398 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
399 >;
400 };
401
402 pinctrl_ov5640: ov5640grp {
403 fsl,pins = <
404 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
405 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
406 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
407 >;
408 };
409
410 pinctrl_pcal6414: pcal6414-gpiogrp {
411 fsl,pins = <
412 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
413 >;
414 };
415
416 pinctrl_pdm: pdmgrp {
417 fsl,pins = <
418 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
419 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
420 >;
421 };
422
423 pinctrl_reg_usb_otg1: usbotg1grp {
424 fsl,pins = <
425 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
426 >;
427 };
428
429 pinctrl_pcie0: pcie0grp {
430 fsl,pins = <
431 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
432 >;
433 };
434
435 pinctrl_sai3: sai3grp {
436 fsl,pins = <
437 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
438 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
439 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
440 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
441 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
442 >;
443 };
444
445 pinctrl_uart2: uart2grp {
446 fsl,pins = <
447 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
448 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
449 >;
450 };
451
452 pinctrl_uart3: uart3grp {
453 fsl,pins = <
454 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
455 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
456 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
457 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
458 >;
459 };
460
461 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
462 fsl,pins = <
463 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
464 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
465 >;
466 };
467
468 pinctrl_usdhc2: usdhc2grp {
469 fsl,pins = <
470 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
471 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
472 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
473 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
474 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
475 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
476 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
477 >;
478 };
479
480 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
481 fsl,pins = <
482 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
483 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
484 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
485 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
486 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
487 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
488 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
489 >;
490 };
491
492 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
493 fsl,pins = <
494 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
495 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
496 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
497 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
498 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
499 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
500 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
501 >;
502 };
503 };
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