1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6 #include "imx8mm-overdrive.dtsi"
7
8 / {
9 aliases {
10 rtc0 = &rtc;
11 rtc1 = &snvs_rtc;
12 };
13
14 usdhc1_pwrseq: usdhc1_pwrseq {
15 compatible = "mmc-pwrseq-simple";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
18 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
19 clocks = <&osc_32k>;
20 clock-names = "ext_clock";
21 post-power-on-delay-ms = <80>;
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0x0 0x40000000 0 0x80000000>;
27 };
28 };
29
30 &A53_0 {
31 cpu-supply = <&buck2_reg>;
32 };
33
34 &A53_1 {
35 cpu-supply = <&buck2_reg>;
36 };
37
38 &A53_2 {
39 cpu-supply = <&buck2_reg>;
40 };
41
42 &A53_3 {
43 cpu-supply = <&buck2_reg>;
44 };
45
46 &ddrc {
47 operating-points-v2 = <&ddrc_opp_table>;
48
49 ddrc_opp_table: opp-table {
50 compatible = "operating-points-v2";
51
52 opp-25000000 {
53 opp-hz = /bits/ 64 <25000000>;
54 };
55
56 opp-100000000 {
57 opp-hz = /bits/ 64 <100000000>;
58 };
59
60 opp-750000000 {
61 opp-hz = /bits/ 64 <750000000>;
62 };
63 };
64 };
65
66 &fec1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_fec1>;
69 phy-mode = "rgmii-id";
70 phy-handle = <ðphy0>;
71 fsl,magic-packet;
72 status = "okay";
73
74 mdio {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 ethphy0: ethernet-phy@0 {
79 compatible = "ethernet-phy-ieee802.3-c22";
80 reg = <0>;
81 };
82 };
83 };
84
85 &flexspi {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_flexspi>;
88 status = "okay";
89
90 flash@0 {
91 reg = <0>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "jedec,spi-nor";
95 spi-max-frequency = <80000000>;
96 spi-tx-bus-width = <1>;
97 spi-rx-bus-width = <4>;
98 };
99 };
100
101 &i2c1 {
102 clock-frequency = <400000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_i2c1>;
105 status = "okay";
106
107 pmic@4b {
108 compatible = "rohm,bd71847";
109 reg = <0x4b>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_pmic>;
112 interrupt-parent = <&gpio1>;
113 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
114 rohm,reset-snvs-powered;
115
116 #clock-cells = <0>;
117 clocks = <&osc_32k>;
118 clock-output-names = "clk-32k-out";
119
120 regulators {
121 buck1_reg: BUCK1 {
122 regulator-name = "buck1";
123 regulator-min-microvolt = <700000>;
124 regulator-max-microvolt = <1300000>;
125 regulator-boot-on;
126 regulator-always-on;
127 regulator-ramp-delay = <1250>;
128 };
129
130 buck2_reg: BUCK2 {
131 regulator-name = "buck2";
132 regulator-min-microvolt = <700000>;
133 regulator-max-microvolt = <1300000>;
134 regulator-boot-on;
135 regulator-always-on;
136 regulator-ramp-delay = <1250>;
137 rohm,dvs-run-voltage = <1000000>;
138 rohm,dvs-idle-voltage = <900000>;
139 };
140
141 buck3_reg: BUCK3 {
142 // BUCK5 in datasheet
143 regulator-name = "buck3";
144 regulator-min-microvolt = <700000>;
145 regulator-max-microvolt = <1350000>;
146 regulator-boot-on;
147 regulator-always-on;
148 };
149
150 buck4_reg: BUCK4 {
151 // BUCK6 in datasheet
152 regulator-name = "buck4";
153 regulator-min-microvolt = <3000000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 buck5_reg: BUCK5 {
160 // BUCK7 in datasheet
161 regulator-name = "buck5";
162 regulator-min-microvolt = <1605000>;
163 regulator-max-microvolt = <1995000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 buck6_reg: BUCK6 {
169 // BUCK8 in datasheet
170 regulator-name = "buck6";
171 regulator-min-microvolt = <800000>;
172 regulator-max-microvolt = <1400000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 ldo1_reg: LDO1 {
178 regulator-name = "ldo1";
179 regulator-min-microvolt = <1600000>;
180 regulator-max-microvolt = <3300000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 ldo2_reg: LDO2 {
186 regulator-name = "ldo2";
187 regulator-min-microvolt = <800000>;
188 regulator-max-microvolt = <900000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo3_reg: LDO3 {
194 regulator-name = "ldo3";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3300000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 ldo4_reg: LDO4 {
202 regulator-name = "ldo4";
203 regulator-min-microvolt = <900000>;
204 regulator-max-microvolt = <1800000>;
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 ldo6_reg: LDO6 {
210 regulator-name = "ldo6";
211 regulator-min-microvolt = <900000>;
212 regulator-max-microvolt = <1800000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216 };
217 };
218 };
219
220 &i2c3 {
221 clock-frequency = <400000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c3>;
224 status = "okay";
225
226 eeprom@50 {
227 compatible = "microchip,24c64", "atmel,24c64";
228 pagesize = <32>;
229 read-only; /* Manufacturing EEPROM programmed at factory */
230 reg = <0x50>;
231 };
232
233 rtc: rtc@51 {
234 compatible = "nxp,pcf85263";
235 reg = <0x51>;
236 };
237 };
238
239 &uart1 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_uart1>;
242 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
243 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
244 uart-has-rtscts;
245 status = "okay";
246
247 bluetooth {
248 compatible = "brcm,bcm43438-bt";
249 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
250 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
251 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
252 clocks = <&osc_32k>;
253 max-speed = <4000000>;
254 clock-names = "extclk";
255 };
256 };
257
258 &usdhc1 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 pinctrl-names = "default", "state_100mhz", "state_200mhz";
262 pinctrl-0 = <&pinctrl_usdhc1>;
263 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
264 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
265 bus-width = <4>;
266 non-removable;
267 cap-power-off-card;
268 keep-power-in-suspend;
269 mmc-pwrseq = <&usdhc1_pwrseq>;
270 status = "okay";
271
272 brcmf: bcrmf@1 {
273 reg = <1>;
274 compatible = "brcm,bcm4329-fmac";
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_wlan>;
277 interrupt-parent = <&gpio2>;
278 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "host-wake";
280 };
281 };
282
283 &usdhc3 {
284 pinctrl-names = "default", "state_100mhz", "state_200mhz";
285 pinctrl-0 = <&pinctrl_usdhc3>;
286 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
287 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
288 bus-width = <8>;
289 non-removable;
290 status = "okay";
291 };
292
293 &wdog1 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_wdog>;
296 fsl,ext-reset-output;
297 status = "okay";
298 };
299
300 &iomuxc {
301 pinctrl_fec1: fec1grp {
302 fsl,pins = <
303 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
304 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
305 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
306 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
307 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
308 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
309 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
310 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
311 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
312 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
313 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
314 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
315 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
316 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
317 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
318 >;
319 };
320
321 pinctrl_i2c1: i2c1grp {
322 fsl,pins = <
323 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
324 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
325 >;
326 };
327
328 pinctrl_i2c3: i2c3grp {
329 fsl,pins = <
330 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
331 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
332 >;
333 };
334
335 pinctrl_flexspi: flexspigrp {
336 fsl,pins = <
337 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
338 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
339 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
340 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
341 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
342 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
343 >;
344 };
345
346 pinctrl_pmic: pmicirqgrp {
347 fsl,pins = <
348 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
349 >;
350 };
351
352 pinctrl_uart1: uart1grp {
353 fsl,pins = <
354 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
355 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
356 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
357 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
358 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
359 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
360 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
361 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
362 >;
363 };
364
365 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
366 fsl,pins = <
367 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
368 >;
369 };
370
371 pinctrl_usdhc1: usdhc1grp {
372 fsl,pins = <
373 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
374 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
375 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
376 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
377 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
378 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
379 >;
380 };
381
382 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
383 fsl,pins = <
384 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
385 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
386 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
387 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
388 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
389 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
390 >;
391 };
392
393 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
394 fsl,pins = <
395 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
396 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
397 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
398 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
399 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
400 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
401 >;
402 };
403
404 pinctrl_usdhc3: usdhc3grp {
405 fsl,pins = <
406 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
407 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
408 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
409 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
410 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
411 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
412 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
413 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
414 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
415 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
416 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
417 >;
418 };
419
420 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
421 fsl,pins = <
422 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
423 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
424 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
425 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
426 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
427 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
428 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
429 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
430 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
431 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
432 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
433 >;
434 };
435
436 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
437 fsl,pins = <
438 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
439 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
440 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
441 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
442 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
443 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
444 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
445 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
446 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
447 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
448 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
449 >;
450 };
451
452 pinctrl_wdog: wdoggrp {
453 fsl,pins = <
454 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
455 >;
456 };
457
458 pinctrl_wlan: wlangrp {
459 fsl,pins = <
460 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
461 >;
462 };
463 };
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