1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6 /dts-v1/;
7
8 #include "imx8mm-kontron-osm-s.dtsi"
9
10 / {
11 model = "Kontron BL i.MX8MM OSM-S (N802X S)";
12 compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
13
14 aliases {
15 ethernet1 = &usbnet;
16 };
17
18 /* fixed crystal dedicated to mcp2542fd */
19 osc_can: clock-osc-can {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <40000000>;
23 clock-output-names = "osc-can";
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 led1 {
30 label = "led1";
31 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
32 linux,default-trigger = "heartbeat";
33 };
34
35 led2 {
36 label = "led2";
37 gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
38 };
39
40 led3 {
41 label = "led3";
42 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
43 };
44 };
45
46 pwm-beeper {
47 compatible = "pwm-beeper";
48 pwms = <&pwm2 0 5000 0>;
49 };
50
51 reg_rst_eth2: regulator-rst-eth2 {
52 compatible = "regulator-fixed";
53 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 regulator-always-on;
56 regulator-name = "rst-usb-eth2";
57 };
58
59 reg_vdd_5v: regulator-5v {
60 compatible = "regulator-fixed";
61 regulator-always-on;
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 regulator-name = "vdd-5v";
65 };
66 };
67
68 &ecspi2 {
69 status = "okay";
70
71 can@0 {
72 compatible = "microchip,mcp251xfd";
73 reg = <0>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_can>;
76 clocks = <&osc_can>;
77 interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
78 /*
79 * Limit the SPI clock to 15 MHz to prevent issues
80 * with corrupted data due to chip errata.
81 */
82 spi-max-frequency = <15000000>;
83 vdd-supply = <®_vdd_3v3>;
84 xceiver-supply = <®_vdd_5v>;
85 };
86 };
87
88 &ecspi3 {
89 status = "okay";
90
91 eeram@0 {
92 compatible = "microchip,48l640";
93 reg = <0>;
94 spi-max-frequency = <20000000>;
95 };
96 };
97
98 &fec1 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_enet_rgmii>;
101 phy-connection-type = "rgmii-id";
102 phy-handle = <ðphy>;
103 status = "okay";
104
105 mdio {
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 ethphy: ethernet-phy@0 {
110 compatible = "ethernet-phy-id4f51.e91b";
111 reg = <0>;
112 reset-assert-us = <10000>;
113 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
114 };
115 };
116 };
117
118 /*
119 * Rename SoM signals according to board usage:
120 * GPIO_B_0 -> DIO1_OUT
121 * GPIO_B_1 -> DIO2_OUT
122 */
123 &gpio1 {
124 gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
125 "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
126 "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT",
127 "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
128 "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
129 "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
130 "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
131 "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
132 "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
133 "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
134 "ETH_A_(R)(G)MII_RXD3";
135 };
136
137 /*
138 * Rename SoM signals according to board usage:
139 * GPIO_B_2 -> DIO3_OUT
140 * GPIO_B_3 -> DIO4_OUT
141 */
142 &gpio3 {
143 gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
144 "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
145 "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
146 "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
147 "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT",
148 "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#",
149 "PCIe_WAKE#", "USB_A_EN";
150 };
151
152 /*
153 * Rename SoM signals according to board usage:
154 * GPIO_B_4 -> DIO1_IN
155 * GPIO_B_5 -> DIO2_IN
156 * GPIO_B_6 -> DIO3_IN
157 * GPIO_B_7 -> DIO4_IN
158 */
159 &gpio4 {
160 gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
161 "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "",
162 "", "", "I2S_LRCLK", "I2S_BITCLK",
163 "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN",
164 "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
165 "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
166 "UART_A_RTS", "", "", "",
167 "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
168 };
169
170 &i2c3 {
171 status = "okay";
172
173 usb-hub@2c {
174 compatible = "microchip,usb2514b";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_usb_hub>;
177 reg = <0x2c>;
178 non-removable-ports = <0>, <3>;
179 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
180 };
181 };
182
183 &pwm2 {
184 status = "okay";
185 };
186
187 ®_usb2_vbus {
188 status = "disabled";
189 };
190
191 ®_usdhc2_vcc {
192 status = "disabled";
193 };
194
195 ®_usdhc3_vcc {
196 status = "disabled";
197 };
198
199 &uart1 {
200 uart-has-rtscts;
201 status = "okay";
202 };
203
204 &uart2 {
205 linux,rs485-enabled-at-boot-time;
206 uart-has-rtscts;
207 status = "okay";
208 };
209
210 &usbotg1 {
211 dr_mode = "otg";
212 status = "okay";
213 };
214
215 &usbotg2 {
216 dr_mode = "host";
217 disable-over-current;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 status = "okay";
221
222 /* VBUS is controlled by the hub */
223 /delete-property/ vbus-supply;
224
225 usb1@1 {
226 compatible = "usb424,2514";
227 reg = <1>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 usbnet: ethernet@1 {
232 compatible = "usbb95,772b";
233 reg = <1>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 };
236 };
237 };
238
239 &usdhc2 {
240 vmmc-supply = <®_vdd_3v3>;
241 status = "okay";
242 };
243
244 &iomuxc {
245 pinctrl_can: cangrp {
246 fsl,pins = <
247 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
248 >;
249 };
250
251 pinctrl_usb_hub: usbhubgrp {
252 fsl,pins = <
253 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
254 >;
255 };
256 };
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