1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "imx8mm.dtsi"
9
10 / {
11 model = "Kontron OSM-S i.MX8MM (N802X SOM)";
12 compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
13
14 aliases {
15 rtc0 = &rv3028;
16 rtc1 = &snvs_rtc;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 /*
22 * There are multiple SoM flavors with different DDR sizes.
23 * The smallest is 1GB. For larger sizes the bootloader will
24 * update the reg property.
25 */
26 reg = <0x0 0x40000000 0 0x80000000>;
27 };
28
29 chosen {
30 stdout-path = &uart3;
31 };
32
33 reg_vdd_carrier: regulator-vdd-carrier {
34 compatible = "regulator-fixed";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
37 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 regulator-always-on;
40 regulator-boot-on;
41 regulator-name = "VDD_CARRIER";
42
43 regulator-state-standby {
44 regulator-on-in-suspend;
45 };
46
47 regulator-state-mem {
48 regulator-off-in-suspend;
49 };
50
51 regulator-state-disk {
52 regulator-off-in-suspend;
53 };
54 };
55
56 reg_usb1_vbus: regulator-usb1-vbus {
57 compatible = "regulator-fixed";
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
60 enable-active-high;
61 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 regulator-name = "VBUS_USB1";
65 };
66
67 reg_usb2_vbus: regulator-usb2-vbus {
68 compatible = "regulator-fixed";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_reg_usb2_vbus>;
71 enable-active-high;
72 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 regulator-name = "VBUS_USB2";
76 };
77
78 reg_usdhc2_vcc: regulator-usdhc2-vcc {
79 compatible = "regulator-fixed";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
82 enable-active-high;
83 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-name = "VCC_SDIO_A";
87 };
88
89 reg_usdhc3_vcc: regulator-usdhc3-vcc {
90 compatible = "regulator-fixed";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>;
93 enable-active-high;
94 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 regulator-name = "VCC_SDIO_B";
98 };
99 };
100
101 &A53_0 {
102 cpu-supply = <®_vdd_arm>;
103 };
104
105 &A53_1 {
106 cpu-supply = <®_vdd_arm>;
107 };
108
109 &A53_2 {
110 cpu-supply = <®_vdd_arm>;
111 };
112
113 &A53_3 {
114 cpu-supply = <®_vdd_arm>;
115 };
116
117 &ddrc {
118 operating-points-v2 = <&ddrc_opp_table>;
119
120 ddrc_opp_table: opp-table {
121 compatible = "operating-points-v2";
122
123 opp-100000000 {
124 opp-hz = /bits/ 64 <100000000>;
125 };
126
127 opp-750000000 {
128 opp-hz = /bits/ 64 <750000000>;
129 };
130 };
131 };
132
133 &ecspi1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_ecspi1>;
136 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
137 status = "okay";
138
139 flash@0 {
140 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
141 spi-max-frequency = <80000000>;
142 reg = <0>;
143
144 partitions {
145 compatible = "fixed-partitions";
146 #address-cells = <1>;
147 #size-cells = <1>;
148
149 partition@0 {
150 label = "u-boot";
151 reg = <0x0 0x1e0000>;
152 };
153
154 partition@1e0000 {
155 label = "env";
156 reg = <0x1e0000 0x10000>;
157 };
158
159 partition@1f0000 {
160 label = "env_redundant";
161 reg = <0x1f0000 0x10000>;
162 };
163 };
164 };
165 };
166
167 &ecspi2 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>;
170 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
171 };
172
173 &ecspi3 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_ecspi3>;
176 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
177 };
178
179 &gpio1 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_gpio1>;
182 gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
183 "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
184 "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0",
185 "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
186 "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
187 "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
188 "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
189 "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
190 "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
191 "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
192 "ETH_A_(R)(G)MII_RXD3";
193 };
194
195 &gpio2 {
196 gpio-line-names = "", "", "", "",
197 "", "", "", "",
198 "", "", "", "",
199 "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
200 "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",
201 "SDIO_A_WP";
202 };
203
204 &gpio3 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_gpio3>;
207 gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
208 "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
209 "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
210 "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
211 "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2",
212 "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#",
213 "PCIe_WAKE#", "USB_A_EN";
214 };
215
216 &gpio4 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_gpio4>;
219 gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
220 "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "",
221 "", "", "I2S_LRCLK", "I2S_BITCLK",
222 "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6",
223 "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
224 "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
225 "UART_A_RTS", "", "", "",
226 "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
227 };
228
229 &gpio5 {
230 gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2",
231 "PWM_1", "PWM_0", "", "",
232 "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)",
233 "SPI_A_SCK", "SPI_A_CS0#", "", "",
234 "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA",
235 "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO",
236 "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX",
237 "UART_C_RX", "UART_C_TX";
238 };
239
240 &i2c1 {
241 clock-frequency = <400000>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c1>;
244 status = "okay";
245
246 pca9450: pmic@25 {
247 compatible = "nxp,pca9450a";
248 reg = <0x25>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_pmic>;
251 interrupt-parent = <&gpio1>;
252 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
253
254 regulators {
255 reg_vdd_soc: BUCK1 {
256 regulator-name = "+0V8_VDD_SOC (BUCK1)";
257 regulator-min-microvolt = <800000>;
258 regulator-max-microvolt = <850000>;
259 regulator-boot-on;
260 regulator-always-on;
261 regulator-ramp-delay = <3125>;
262 nxp,dvs-run-voltage = <850000>;
263 nxp,dvs-standby-voltage = <800000>;
264 };
265
266 reg_vdd_arm: BUCK2 {
267 regulator-name = "+0V9_VDD_ARM (BUCK2)";
268 regulator-min-microvolt = <850000>;
269 regulator-max-microvolt = <950000>;
270 regulator-boot-on;
271 regulator-always-on;
272 regulator-ramp-delay = <3125>;
273 nxp,dvs-run-voltage = <950000>;
274 nxp,dvs-standby-voltage = <850000>;
275 };
276
277 reg_vdd_dram: BUCK3 {
278 regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
279 regulator-min-microvolt = <850000>;
280 regulator-max-microvolt = <950000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 reg_vdd_3v3: BUCK4 {
286 regulator-name = "+3V3 (BUCK4)";
287 regulator-min-microvolt = <3300000>;
288 regulator-max-microvolt = <3300000>;
289 regulator-boot-on;
290 regulator-always-on;
291 };
292
293 reg_vdd_1v8: BUCK5 {
294 regulator-name = "+1V8 (BUCK5)";
295 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <1800000>;
297 regulator-boot-on;
298 regulator-always-on;
299 };
300
301 reg_nvcc_dram: BUCK6 {
302 regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
303 regulator-min-microvolt = <1100000>;
304 regulator-max-microvolt = <1100000>;
305 regulator-boot-on;
306 regulator-always-on;
307 };
308
309 reg_nvcc_snvs: LDO1 {
310 regulator-name = "+1V8_NVCC_SNVS (LDO1)";
311 regulator-min-microvolt = <1800000>;
312 regulator-max-microvolt = <1800000>;
313 regulator-boot-on;
314 regulator-always-on;
315 };
316
317 reg_vdd_snvs: LDO2 {
318 regulator-name = "+0V8_VDD_SNVS (LDO2)";
319 regulator-min-microvolt = <800000>;
320 regulator-max-microvolt = <900000>;
321 regulator-boot-on;
322 regulator-always-on;
323 };
324
325 reg_vdda: LDO3 {
326 regulator-name = "+1V8_VDDA (LDO3)";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-boot-on;
330 regulator-always-on;
331 };
332
333 reg_vdd_phy: LDO4 {
334 regulator-name = "+0V9_VDD_PHY (LDO4)";
335 regulator-min-microvolt = <900000>;
336 regulator-max-microvolt = <900000>;
337 regulator-boot-on;
338 regulator-always-on;
339 };
340
341 reg_nvcc_sd: LDO5 {
342 regulator-name = "NVCC_SD (LDO5)";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <3300000>;
345 };
346 };
347 };
348
349 eeprom: eeprom@50 {
350 compatible = "atmel,24c64";
351 reg = <0x50>;
352 address-width = <16>;
353 pagesize = <32>;
354 size = <8192>;
355 };
356
357 rv3028: rtc@52 {
358 compatible = "microcrystal,rv3028";
359 reg = <0x52>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_rtc>;
362 interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>;
363 };
364 };
365
366 &i2c2 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_i2c2>;
369 };
370
371 &i2c3 {
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_i2c3>;
374 };
375
376 &i2c4 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_i2c4>;
379 };
380
381 &pwm1 {
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_pwm1>;
384 };
385
386 &pwm2 {
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_pwm2>;
389 };
390
391 &pwm3 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_pwm3>;
394 };
395
396 &uart1 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_uart1>;
399 };
400
401 &uart2 {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_uart2>;
404 };
405
406 &uart3 { /* console */
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart3>;
409 status = "okay";
410 };
411
412 &uart4 {
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_uart4>;
415 };
416
417 &usbotg1 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_usb1>;
420 vbus-supply = <®_usb1_vbus>;
421 };
422
423 &usbotg2 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usb2>;
426 vbus-supply = <®_usb2_vbus>;
427 };
428
429 &usdhc1 {
430 pinctrl-names = "default", "state_100mhz", "state_200mhz";
431 pinctrl-0 = <&pinctrl_usdhc1>;
432 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
433 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
434 vmmc-supply = <®_vdd_3v3>;
435 vqmmc-supply = <®_vdd_1v8>;
436 bus-width = <8>;
437 non-removable;
438 status = "okay";
439 };
440
441 &usdhc2 {
442 pinctrl-names = "default", "state_100mhz", "state_200mhz";
443 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
444 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
445 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
446 vmmc-supply = <®_usdhc2_vcc>;
447 vqmmc-supply = <®_nvcc_sd>;
448 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
449 };
450
451 &usdhc3 {
452 pinctrl-names = "default", "state_100mhz", "state_200mhz";
453 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
454 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
455 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
456 vmmc-supply = <®_usdhc3_vcc>;
457 vqmmc-supply = <®_nvcc_sd>;
458 cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
459 };
460
461 &wdog1 {
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_wdog>;
464 fsl,ext-reset-output;
465 status = "okay";
466 };
467
468 &iomuxc {
469 pinctrl_csi_mck: csimckgrp {
470 fsl,pins = <
471 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */
472 >;
473 };
474
475 pinctrl_ecspi1: ecspi1grp {
476 fsl,pins = <
477 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
478 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
479 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
480 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
481 >;
482 };
483
484 pinctrl_ecspi2: ecspi2grp {
485 fsl,pins = <
486 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */
487 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */
488 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */
489 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */
490 >;
491 };
492
493 pinctrl_ecspi2_gpio: ecspi2gpiogrp {
494 fsl,pins = <
495 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */
496 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */
497 >;
498 };
499
500 pinctrl_ecspi3: ecspi3grp {
501 fsl,pins = <
502 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */
503 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */
504 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */
505 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */
506 >;
507 };
508
509 pinctrl_enet_rgmii: enetrgmiigrp {
510 fsl,pins = <
511 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
512 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
513 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */
514 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */
515 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */
516 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */
517 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
518 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
519 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */
520 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */
521 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
522 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */
523 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
524 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */
525 >;
526 };
527
528 pinctrl_enet_rmii: enetrmiigrp {
529 fsl,pins = <
530 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
531 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
532 MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */
533 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */
534 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */
535 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */
536 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */
537 MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */
538 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
539 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */
540 >;
541 };
542
543 pinctrl_gpio1: gpio1grp {
544 fsl,pins = <
545 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */
546 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */
547 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */
548 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */
549 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */
550 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */
551 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */
552 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */
553 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */
554 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */
555 >;
556 };
557
558 pinctrl_gpio3: gpio3grp {
559 fsl,pins = <
560 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */
561 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */
562 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */
563 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */
564 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */
565 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */
566 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */
567 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */
568 >;
569 };
570
571 pinctrl_gpio4: gpio4grp {
572 fsl,pins = <
573 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */
574 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */
575 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */
576 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */
577 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */
578 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */
579 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */
580 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */
581 >;
582 };
583
584 pinctrl_i2c1: i2c1grp {
585 fsl,pins = <
586 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
587 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
588 >;
589 };
590
591 pinctrl_i2c2: i2c2grp {
592 fsl,pins = <
593 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */
594 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */
595 >;
596 };
597
598 pinctrl_i2c3: i2c3grp {
599 fsl,pins = <
600 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */
601 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */
602 >;
603 };
604
605 pinctrl_i2c4: i2c4grp {
606 fsl,pins = <
607 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */
608 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */
609 >;
610 };
611
612 pinctrl_pcie: pciegrp {
613 fsl,pins = <
614 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */
615 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */
616 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */
617 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */
618 >;
619 };
620
621 pinctrl_pmic: pmicgrp {
622 fsl,pins = <
623 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
624 >;
625 };
626
627 pinctrl_pwm1: pwm1grp {
628 fsl,pins = <
629 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */
630 >;
631 };
632
633 pinctrl_pwm2: pwm2grp {
634 fsl,pins = <
635 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */
636 >;
637 };
638
639 pinctrl_pwm3: pwm3grp {
640 fsl,pins = <
641 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */
642 >;
643 };
644
645 pinctrl_reg_usb1_vbus: regusb1vbusgrp {
646 fsl,pins = <
647 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */
648 >;
649 };
650
651 pinctrl_reg_usb2_vbus: regusb2vbusgrp {
652 fsl,pins = <
653 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */
654 >;
655 };
656
657 pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {
658 fsl,pins = <
659 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */
660 >;
661 };
662
663 pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {
664 fsl,pins = <
665 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
666 >;
667 };
668
669 pinctrl_reg_vdd_carrier: regvddcarriergrp {
670 fsl,pins = <
671 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */
672 >;
673 };
674
675 pinctrl_rtc: rtcgrp {
676 fsl,pins = <
677 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
678 >;
679 };
680
681 pinctrl_sai1: sai1grp {
682 fsl,pins = <
683 MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */
684 MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */
685 MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */
686 MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */
687 MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */
688 MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */
689 MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */
690 >;
691 };
692
693 pinctrl_uart1: uart1grp {
694 fsl,pins = <
695 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */
696 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */
697 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */
698 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */
699 >;
700 };
701
702 pinctrl_uart2: uart2grp {
703 fsl,pins = <
704 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */
705 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */
706 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */
707 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */
708 >;
709 };
710
711 pinctrl_uart3: uart3grp {
712 fsl,pins = <
713 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */
714 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */
715 >;
716 };
717
718 pinctrl_uart4: uart4grp {
719 fsl,pins = <
720 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */
721 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */
722 >;
723 };
724
725 pinctrl_usb1: usb1grp {
726 fsl,pins = <
727 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */
728 >;
729 };
730
731 pinctrl_usb2: usb2grp {
732 fsl,pins = <
733 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */
734 >;
735 };
736
737 pinctrl_usdhc1: usdhc1grp {
738 fsl,pins = <
739 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
740 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
741 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
742 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
743 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
744 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
745 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
746 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
747 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
748 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
749 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
750 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
751 >;
752 };
753
754 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
755 fsl,pins = <
756 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
757 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
758 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
759 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
760 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
761 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
762 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
763 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
764 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
765 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
766 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
767 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
768 >;
769 };
770
771 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
772 fsl,pins = <
773 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
774 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
775 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
776 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
777 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
778 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
779 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
780 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
781 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
782 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
783 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
784 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
785 >;
786 };
787
788 pinctrl_usdhc2: usdhc2grp {
789 fsl,pins = <
790 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */
791 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */
792 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */
793 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
794 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
795 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
796 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
797 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
798 >;
799 };
800
801 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
802 fsl,pins = <
803 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */
804 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */
805 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */
806 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
807 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
808 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
809 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
810 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
811 >;
812 };
813
814 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
815 fsl,pins = <
816 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */
817 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */
818 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */
819 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
820 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
821 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
822 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
823 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
824 >;
825 };
826
827 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
828 fsl,pins = <
829 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */
830 >;
831 };
832
833 pinctrl_usdhc3: usdhc3grp {
834 fsl,pins = <
835 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */
836 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */
837 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */
838 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */
839 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */
840 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */
841 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */
842 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */
843 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */
844 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */
845 >;
846 };
847
848 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
849 fsl,pins = <
850 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */
851 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */
852 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */
853 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */
854 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */
855 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */
856 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */
857 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */
858 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */
859 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */
860 >;
861 };
862
863 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
864 fsl,pins = <
865 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */
866 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */
867 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */
868 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */
869 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */
870 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */
871 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */
872 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */
873 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */
874 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */
875 >;
876 };
877
878 pinctrl_usdhc3_gpio: usdhc3gpiogrp {
879 fsl,pins = <
880 MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */
881 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
882 >;
883 };
884
885 pinctrl_wdog: wdoggrp {
886 fsl,pins = <
887 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
888 >;
889 };
890 };
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