1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 #include "imx8mm-phycore-som.dtsi"
12
13 / {
14 model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
15 compatible = "phytec,imx8mm-phygate-tauri-l",
16 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
17
18 chosen {
19 stdout-path = &uart3;
20 };
21
22 can_osc_40m: clock-can {
23 compatible = "fixed-clock";
24 clock-frequency = <40000000>;
25 clock-output-names = "can_osc_40m";
26 #clock-cells = <0>;
27 };
28
29 gpio-keys {
30 compatible = "gpio-keys";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpiokeys>;
33
34 key {
35 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
36 label = "KEY-A";
37 linux,code = <KEY_A>;
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_leds>;
45
46 led-1 {
47 color = <LED_COLOR_ID_RED>;
48 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
49 linux,default-trigger = "none";
50 };
51
52 led-2 {
53 color = <LED_COLOR_ID_YELLOW>;
54 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
55 linux,default-trigger = "none";
56 };
57 };
58
59 usdhc1_pwrseq: pwr-seq {
60 compatible = "mmc-pwrseq-simple";
61 post-power-on-delay-ms = <100>;
62 power-off-delay-us = <60>;
63 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
64 };
65
66 reg_usb_hub_vbus: regulator-hub-otg1 {
67 compatible = "regulator-fixed";
68 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
69 enable-active-high;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_usbhubpwr>;
72 regulator-name = "usb_hub_vbus";
73 regulator-max-microvolt = <5000000>;
74 regulator-min-microvolt = <5000000>;
75 };
76
77 reg_usb_otg1_vbus: regulator-usb-otg1 {
78 compatible = "regulator-fixed";
79 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
80 enable-active-high;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usbotg1pwr>;
83 regulator-name = "usb_otg1_vbus";
84 regulator-max-microvolt = <5000000>;
85 regulator-min-microvolt = <5000000>;
86 };
87
88 reg_usdhc2_vmmc: regulator-usdhc2 {
89 compatible = "regulator-fixed";
90 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
91 enable-active-high;
92 off-on-delay-us = <20000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
95 regulator-max-microvolt = <3300000>;
96 regulator-min-microvolt = <3300000>;
97 regulator-name = "VSD_3V3";
98 };
99 };
100
101 &ecspi1 {
102 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
103 <&gpio5 13 GPIO_ACTIVE_LOW>,
104 <&gpio5 2 GPIO_ACTIVE_LOW>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 status = "okay";
110
111 /* CAN MCP251XFD */
112 can0: can@0 {
113 compatible = "microchip,mcp251xfd";
114 reg = <0>;
115 clocks = <&can_osc_40m>;
116 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
117 interrupt-parent = <&gpio1>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_can_int>;
120 spi-max-frequency = <10000000>;
121 };
122
123 tpm: tpm@1 {
124 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
125 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
126 interrupt-parent = <&gpio2>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_tpm>;
129 reg = <1>;
130 spi-max-frequency = <38000000>;
131 };
132 };
133
134 &i2c2 {
135 clock-frequency = <400000>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_i2c2>;
138 pinctrl-1 = <&pinctrl_i2c2_gpio>;
139 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
140 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
141 status = "okay";
142
143 temp_sense0: temperature-sensor@49 {
144 compatible = "ti,tmp102";
145 reg = <0x49>;
146 interrupt-parent = <&gpio4>;
147 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_tempsense>;
150 #thermal-sensor-cells = <1>;
151 };
152 };
153
154 &i2c3 {
155 clock-frequency = <400000>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c3>;
158 pinctrl-1 = <&pinctrl_i2c3_gpio>;
159 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
160 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
161 status = "okay";
162 };
163
164 &i2c4 {
165 clock-frequency = <400000>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c4>;
168 pinctrl-1 = <&pinctrl_i2c4_gpio>;
169 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
170 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
171 status = "okay";
172 };
173
174 /* PCIe */
175 &pcie0 {
176 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
177 <&clk IMX8MM_CLK_PCIE1_PHY>,
178 <&clk IMX8MM_CLK_PCIE1_CTRL>;
179 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
180 <&clk IMX8MM_SYS_PLL2_100M>,
181 <&clk IMX8MM_SYS_PLL2_250M>;
182 assigned-clock-rates = <10000000>, <100000000>, <250000000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_pcie>;
185 reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
186 status = "okay";
187 };
188
189 &pcie_phy {
190 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
191 fsl,clkreq-unsupported;
192 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
193 fsl,tx-deemph-gen1 = <0x2d>;
194 fsl,tx-deemph-gen2 = <0xf>;
195 status = "okay";
196 };
197
198 &pwm1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_pwm1>;
201 status = "okay";
202 };
203
204 &pwm3 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_pwm3>;
207 status = "okay";
208 };
209
210 &pwm4 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_pwm4>;
213 status = "okay";
214 };
215
216 /* RTC */
217 &rv3028 {
218 aux-voltage-chargeable = <1>;
219 trickle-resistor-ohms = <3000>;
220 };
221
222 &uart1 {
223 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
224 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_uart1>;
227 status = "okay";
228 };
229
230 /* UART2 - RS232 */
231 &uart2 {
232 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
233 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart2>;
236 status = "okay";
237 };
238
239 /* UART - console */
240 &uart3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart3>;
243 status = "okay";
244 };
245
246 /* USB */
247 &usbotg1 {
248 adp-disable;
249 dr_mode = "otg";
250 over-current-active-low;
251 samsung,picophy-pre-emp-curr-control = <3>;
252 samsung,picophy-dc-vol-level-adjust = <7>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_usbotg1>;
255 srp-disable;
256 vbus-supply = <®_usb_otg1_vbus>;
257 status = "okay";
258 };
259
260 &usbotg2 {
261 disable-over-current;
262 dr_mode = "host";
263 samsung,picophy-pre-emp-curr-control = <3>;
264 samsung,picophy-dc-vol-level-adjust = <7>;
265 vbus-supply = <®_usb_hub_vbus>;
266 status = "okay";
267 };
268
269 /* SD-Card */
270 &usdhc2 {
271 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
272 assigned-clock-rates = <200000000>;
273 bus-width = <4>;
274 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
275 disable-wp;
276 pinctrl-names = "default", "state_100mhz", "state_200mhz";
277 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
278 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
279 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
280 vmmc-supply = <®_usdhc2_vmmc>;
281 vqmmc-supply = <®_nvcc_sd2>;
282 status = "okay";
283 };
284
285 &iomuxc {
286 pinctrl_can_int: can-intgrp {
287 fsl,pins = <
288 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
289 >;
290 };
291
292 pinctrl_ecspi1: ecspi1grp {
293 fsl,pins = <
294 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
295 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
296 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
297 >;
298 };
299
300 pinctrl_ecspi1_cs: ecspi1csgrp {
301 fsl,pins = <
302 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
303 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
304 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
305 >;
306 };
307
308 pinctrl_gpiokeys: keygrp {
309 fsl,pins = <
310 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
311 >;
312 };
313
314 pinctrl_i2c2: i2c2grp {
315 fsl,pins = <
316 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
317 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
318 >;
319 };
320
321 pinctrl_i2c2_gpio: i2c2gpiogrp {
322 fsl,pins = <
323 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
324 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
325 >;
326 };
327
328
329 pinctrl_i2c3: i2c3grp {
330 fsl,pins = <
331 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
332 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
333 >;
334 };
335
336 pinctrl_i2c3_gpio: i2c3gpiogrp {
337 fsl,pins = <
338 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
339 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
340 >;
341 };
342
343 pinctrl_i2c4: i2c4grp {
344 fsl,pins = <
345 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
346 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
347 >;
348 };
349
350 pinctrl_i2c4_gpio: i2c4gpiogrp {
351 fsl,pins = <
352 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
353 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
354 >;
355 };
356
357 pinctrl_leds: leds1grp {
358 fsl,pins = <
359 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
360 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
361 >;
362 };
363
364 pinctrl_pcie: pciegrp {
365 fsl,pins = <
366 /* COEX2 */
367 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
368 /* COEX1 */
369 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
370 >;
371 };
372
373 pinctrl_pwm1: pwm1grp {
374 fsl,pins = <
375 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
376 >;
377 };
378
379 pinctrl_pwm3: pwm3grp {
380 fsl,pins = <
381 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
382 >;
383 };
384
385 pinctrl_pwm4: pwm4grp {
386 fsl,pins = <
387 MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
388 >;
389 };
390
391 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
392 fsl,pins = <
393 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
394 >;
395 };
396
397 pinctrl_tempsense: tempsensegrp {
398 fsl,pins = <
399 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
400 >;
401 };
402
403 pinctrl_tpm: tpmgrp {
404 fsl,pins = <
405 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
406 >;
407 };
408
409 pinctrl_uart1: uart1grp {
410 fsl,pins = <
411 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
412 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
413 >;
414 };
415
416 pinctrl_uart2: uart2grp {
417 fsl,pins = <
418 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
419 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
420 >;
421 };
422
423 pinctrl_uart3: uart3grp {
424 fsl,pins = <
425 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
426 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
427 >;
428 };
429
430 pinctrl_usbhubpwr: usbhubpwrgrp {
431 fsl,pins = <
432 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
433 >;
434 };
435
436 pinctrl_usbotg1pwr: usbotg1pwrgrp {
437 fsl,pins = <
438 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
439 >;
440 };
441
442 pinctrl_usbotg1: usbotg1grp {
443 fsl,pins = <
444 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
445 >;
446 };
447
448 pinctrl_usdhc1: usdhc1grp {
449 fsl,pins = <
450 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
451 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
452 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
453 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
454 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
455 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
456 >;
457 };
458
459 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
460 fsl,pins = <
461 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
462 >;
463 };
464
465 pinctrl_usdhc2: usdhc2grp {
466 fsl,pins = <
467 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
468 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
469 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
470 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
471 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
472 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
473 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
474 >;
475 };
476
477 pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
478 fsl,pins = <
479 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
480 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
481 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
482 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
483 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
484 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
485 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
486 >;
487 };
488
489 pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
490 fsl,pins = <
491 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
492 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
493 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
494 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
495 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
496 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
497 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
498 >;
499 };
500 };
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