1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include "imx8mm.dtsi"
8
9 / {
10 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
11 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
12
13 memory@40000000 {
14 device_type = "memory";
15 /* our minimum RAM config will be 1024 MiB */
16 reg = <0x00000000 0x40000000 0 0x40000000>;
17 };
18
19 /* e-MMC IO, needed for HS modes */
20 reg_vcc1v8: regulator-vcc1v8 {
21 compatible = "regulator-fixed";
22 regulator-name = "TQMA8MXML_VCC1V8";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
25 };
26
27 /* identical to buck4_reg, but should never change */
28 reg_vcc3v3: regulator-vcc3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "TQMA8MXML_VCC3V3";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 };
34
35 reserved-memory {
36 #address-cells = <2>;
37 #size-cells = <2>;
38 ranges;
39
40 /* global autoconfigured region for contiguous allocations */
41 linux,cma {
42 compatible = "shared-dma-pool";
43 reusable;
44 /* 640 MiB */
45 size = <0 0x28000000>;
46 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
47 alloc-ranges = <0 0x40000000 0 0x78000000>;
48 linux,cma-default;
49 };
50 };
51 };
52
53 &A53_0 {
54 cpu-supply = <&buck2_reg>;
55 };
56
57 &flexspi {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexspi>;
60 status = "okay";
61
62 flash0: flash@0 {
63 compatible = "jedec,spi-nor";
64 reg = <0>;
65 spi-max-frequency = <84000000>;
66 spi-tx-bus-width = <1>;
67 spi-rx-bus-width = <4>;
68
69 partitions {
70 compatible = "fixed-partitions";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 };
74 };
75 };
76
77 &gpu_2d {
78 status = "okay";
79 };
80
81 &gpu_3d {
82 status = "okay";
83 };
84
85 &i2c1 {
86 pinctrl-names = "default", "gpio";
87 pinctrl-0 = <&pinctrl_i2c1>;
88 pinctrl-1 = <&pinctrl_i2c1_gpio>;
89 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
90 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
91 status = "okay";
92
93 sensor0: temperature-sensor@1b {
94 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
95 reg = <0x1b>;
96 };
97
98 pca9450: pmic@25 {
99 compatible = "nxp,pca9450a";
100 reg = <0x25>;
101
102 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
103 pinctrl-0 = <&pinctrl_pmic>;
104 pinctrl-names = "default";
105 interrupt-parent = <&gpio1>;
106 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
107
108 regulators {
109 /* V_0V85_SOC: 0.85 */
110 buck1_reg: BUCK1 {
111 regulator-name = "BUCK1";
112 regulator-min-microvolt = <850000>;
113 regulator-max-microvolt = <850000>;
114 regulator-boot-on;
115 regulator-always-on;
116 regulator-ramp-delay = <3125>;
117 };
118
119 /* VDD_ARM */
120 buck2_reg: BUCK2 {
121 regulator-name = "BUCK2";
122 regulator-min-microvolt = <850000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-boot-on;
125 regulator-always-on;
126 nxp,dvs-run-voltage = <950000>;
127 nxp,dvs-standby-voltage = <850000>;
128 regulator-ramp-delay = <3125>;
129 };
130
131 /* V_0V85_GPU / DRAM / VPU */
132 buck3_reg: BUCK3 {
133 regulator-name = "BUCK3";
134 regulator-min-microvolt = <850000>;
135 regulator-max-microvolt = <950000>;
136 regulator-boot-on;
137 regulator-always-on;
138 regulator-ramp-delay = <3125>;
139 };
140
141 /* VCC3V3 -> VMMC, ... must not be changed */
142 buck4_reg: BUCK4 {
143 regulator-name = "BUCK4";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 regulator-boot-on;
147 regulator-always-on;
148 };
149
150 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
151 buck5_reg: BUCK5 {
152 regulator-name = "BUCK5";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 /* V_1V1 -> RAM, ... must not be changed */
160 buck6_reg: BUCK6 {
161 regulator-name = "BUCK6";
162 regulator-min-microvolt = <1100000>;
163 regulator-max-microvolt = <1100000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 /* V_1V8_SNVS */
169 ldo1_reg: LDO1 {
170 regulator-name = "LDO1";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 /* V_0V8_SNVS */
178 ldo2_reg: LDO2 {
179 regulator-name = "LDO2";
180 regulator-min-microvolt = <800000>;
181 regulator-max-microvolt = <850000>;
182 regulator-boot-on;
183 regulator-always-on;
184 };
185
186 /* V_1V8_ANA */
187 ldo3_reg: LDO3 {
188 regulator-name = "LDO3";
189 regulator-min-microvolt = <1800000>;
190 regulator-max-microvolt = <1800000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 /* V_0V9_MIPI */
196 ldo4_reg: LDO4 {
197 regulator-name = "LDO4";
198 regulator-min-microvolt = <900000>;
199 regulator-max-microvolt = <900000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 /* VCC SD IO - switched using SD2 VSELECT */
205 ldo5_reg: LDO5 {
206 regulator-name = "LDO5";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3300000>;
209 };
210 };
211 };
212
213
214 pcf85063: rtc@51 {
215 compatible = "nxp,pcf85063a";
216 reg = <0x51>;
217 quartz-load-femtofarads = <7000>;
218 };
219
220 eeprom1: eeprom@53 {
221 compatible = "nxp,se97b", "atmel,24c02";
222 read-only;
223 reg = <0x53>;
224 pagesize = <16>;
225 vcc-supply = <®_vcc3v3>;
226 };
227
228 eeprom0: eeprom@57 {
229 compatible = "atmel,24c64";
230 reg = <0x57>;
231 pagesize = <32>;
232 vcc-supply = <®_vcc3v3>;
233 };
234 };
235
236 &mipi_dsi {
237 vddcore-supply = <&ldo4_reg>;
238 vddio-supply = <&ldo3_reg>;
239 };
240
241 &pcie_phy {
242 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
243 fsl,clkreq-unsupported;
244 };
245
246 &usdhc3 {
247 pinctrl-names = "default", "state_100mhz", "state_200mhz";
248 pinctrl-0 = <&pinctrl_usdhc3>;
249 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
250 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
251 bus-width = <8>;
252 non-removable;
253 no-sd;
254 no-sdio;
255 vmmc-supply = <®_vcc3v3>;
256 vqmmc-supply = <®_vcc1v8>;
257 status = "okay";
258 };
259
260 /*
261 * Attention:
262 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
263 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
264 */
265 &wdog1 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_wdog>;
268 fsl,ext-reset-output;
269 status = "okay";
270 };
271
272 &iomuxc {
273 pinctrl_flexspi: flexspigrp {
274 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
275 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
276 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
277 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
278 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
279 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
280 };
281
282 pinctrl_i2c1: i2c1grp {
283 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
284 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
285 };
286
287 pinctrl_i2c1_gpio: i2c1gpiogrp {
288 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
289 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
290 };
291
292 pinctrl_pmic: pmicgrp {
293 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
294 };
295
296 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
297 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
298 };
299
300 pinctrl_usdhc3: usdhc3grp {
301 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
302 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
303 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
304 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
305 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
306 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
307 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
308 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
309 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
310 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
311 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
312 /* option USDHC3_RESET_B not defined, only in RM */
313 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
314 };
315
316 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
317 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
318 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
319 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
320 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
321 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
322 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
323 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
324 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
325 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
326 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
327 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
328 /* option USDHC3_RESET_B not defined, only in RM */
329 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
330 };
331
332 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
333 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
334 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
335 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
336 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
337 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
338 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
339 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
340 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
341 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
342 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
343 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
344 /* option USDHC3_RESET_B not defined, only in RM */
345 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
346 };
347
348 pinctrl_wdog: wdoggrp {
349 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
350 };
351 };
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