1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
4 */
5
6 /dts-v1/;
7
8 #include "imx8mm-var-som.dtsi"
9
10 / {
11 model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
12 compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";
13
14 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
15 compatible = "regulator-fixed";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
18 regulator-name = "VSD_3V3";
19 regulator-min-microvolt = <3300000>;
20 regulator-max-microvolt = <3300000>;
21 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
22 enable-active-high;
23 };
24
25 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
26 compatible = "regulator-fixed";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
29 regulator-name = "usb_otg2_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
33 enable-active-high;
34 };
35
36 gpio-keys {
37 compatible = "gpio-keys";
38
39 key-back {
40 label = "Back";
41 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_BACK>;
43 };
44
45 key-home {
46 label = "Home";
47 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_HOME>;
49 };
50
51 key-menu {
52 label = "Menu";
53 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_MENU>;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60
61 led {
62 label = "Heartbeat";
63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67 };
68
69 ðphy {
70 reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
71 };
72
73 &i2c2 {
74 clock-frequency = <400000>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_i2c2>;
77 status = "okay";
78
79 pca9534: gpio@20 {
80 compatible = "nxp,pca9534";
81 reg = <0x20>;
82 gpio-controller;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_pca9534>;
85 interrupt-parent = <&gpio1>;
86 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
87 #gpio-cells = <2>;
88 wakeup-source;
89
90 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
91 usb3-sata-sel-hog {
92 gpio-hog;
93 gpios = <4 GPIO_ACTIVE_HIGH>;
94 output-low;
95 line-name = "usb3_sata_sel";
96 };
97
98 som-vselect-hog {
99 gpio-hog;
100 gpios = <6 GPIO_ACTIVE_HIGH>;
101 output-low;
102 line-name = "som_vselect";
103 };
104
105 enet-sel-hog {
106 gpio-hog;
107 gpios = <7 GPIO_ACTIVE_HIGH>;
108 output-low;
109 line-name = "enet_sel";
110 };
111 };
112
113 extcon_usbotg1: typec@3d {
114 compatible = "nxp,ptn5150";
115 reg = <0x3d>;
116 interrupt-parent = <&gpio1>;
117 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_ptn5150>;
120 };
121 };
122
123 &i2c3 {
124 /* Capacitive touch controller */
125 ft5x06_ts: touchscreen@38 {
126 compatible = "edt,edt-ft5406";
127 reg = <0x38>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_captouch>;
130 interrupt-parent = <&gpio5>;
131 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
132
133 touchscreen-size-x = <800>;
134 touchscreen-size-y = <480>;
135 touchscreen-inverted-x;
136 touchscreen-inverted-y;
137 };
138
139 rtc@68 {
140 compatible = "dallas,ds1337";
141 reg = <0x68>;
142 };
143 };
144
145 /* Header */
146 &uart1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart1>;
149 status = "okay";
150 };
151
152 /* Header */
153 &uart3 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_uart3>;
156 status = "okay";
157 };
158
159 &usbotg1 {
160 disable-over-current;
161 extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
162 };
163
164 &usbotg2 {
165 dr_mode = "host";
166 vbus-supply = <®_usb_otg2_vbus>;
167 srp-disable;
168 hnp-disable;
169 adp-disable;
170 disable-over-current;
171 /delete-property/ usb-role-switch;
172 /*
173 * FIXME: having USB2 enabled hangs the boot just after:
174 * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
175 * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
176 * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
177 * [ 1.977203] hub 1-0:1.0: USB hub found
178 * [ 1.980987] hub 1-0:1.0: 1 port detected
179 */
180 status = "disabled";
181 };
182
183 &pinctrl_fec1 {
184 fsl,pins = <
185 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
186 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
187 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
188 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
189 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
190 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
191 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
192 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
193 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
194 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
195 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
196 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
197 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
198 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
199 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
200 >;
201 };
202
203 &iomuxc {
204 pinctrl_captouch: captouchgrp {
205 fsl,pins = <
206 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
207 >;
208 };
209
210 pinctrl_i2c2: i2c2grp {
211 fsl,pins = <
212 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
213 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
214 >;
215 };
216
217 pinctrl_pca9534: pca9534grp {
218 fsl,pins = <
219 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
220 >;
221 };
222
223 pinctrl_ptn5150: ptn5150grp {
224 fsl,pins = <
225 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
226 >;
227 };
228
229 pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {
230 fsl,pins = <
231 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16
232 >;
233 };
234
235 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
236 fsl,pins = <
237 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
238 >;
239 };
240
241 pinctrl_uart1: uart1grp {
242 fsl,pins = <
243 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
244 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
245 >;
246 };
247
248 pinctrl_uart3: uart3grp {
249 fsl,pins = <
250 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
251 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
252 >;
253 };
254 };
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