1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/net/ti-dp83867.h>
10
11 / {
12 memory@40000000 {
13 device_type = "memory";
14 reg = <0x0 0x40000000 0 0x80000000>;
15 };
16
17 gpio-keys {
18 compatible = "gpio-keys";
19
20 key-user-pb {
21 label = "user_pb";
22 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
23 linux,code = <BTN_0>;
24 };
25
26 key-user-pb1x {
27 label = "user_pb1x";
28 linux,code = <BTN_1>;
29 interrupt-parent = <&gsc>;
30 interrupts = <0>;
31 };
32
33 key-erased {
34 label = "key_erased";
35 linux,code = <BTN_2>;
36 interrupt-parent = <&gsc>;
37 interrupts = <1>;
38 };
39
40 key-eeprom-wp {
41 label = "eeprom_wp";
42 linux,code = <BTN_3>;
43 interrupt-parent = <&gsc>;
44 interrupts = <2>;
45 };
46
47 key-tamper {
48 label = "tamper";
49 linux,code = <BTN_4>;
50 interrupt-parent = <&gsc>;
51 interrupts = <5>;
52 };
53
54 switch-hold {
55 label = "switch_hold";
56 linux,code = <BTN_5>;
57 interrupt-parent = <&gsc>;
58 interrupts = <7>;
59 };
60 };
61 };
62
63 &A53_0 {
64 cpu-supply = <&buck3_reg>;
65 };
66
67 &A53_1 {
68 cpu-supply = <&buck3_reg>;
69 };
70
71 &A53_2 {
72 cpu-supply = <&buck3_reg>;
73 };
74
75 &A53_3 {
76 cpu-supply = <&buck3_reg>;
77 };
78
79 &ddrc {
80 operating-points-v2 = <&ddrc_opp_table>;
81
82 ddrc_opp_table: opp-table {
83 compatible = "operating-points-v2";
84
85 opp-25000000 {
86 opp-hz = /bits/ 64 <25000000>;
87 };
88
89 opp-100000000 {
90 opp-hz = /bits/ 64 <100000000>;
91 };
92
93 opp-750000000 {
94 opp-hz = /bits/ 64 <750000000>;
95 };
96 };
97 };
98
99 &fec1 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_fec1>;
102 phy-mode = "rgmii-id";
103 phy-handle = <ðphy0>;
104 status = "okay";
105
106 mdio {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 ethphy0: ethernet-phy@0 {
111 compatible = "ethernet-phy-ieee802.3-c22";
112 reg = <0>;
113 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
114 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
115 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
116 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
117
118 leds {
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 led@1 {
123 reg = <1>;
124 color = <LED_COLOR_ID_AMBER>;
125 function = LED_FUNCTION_LAN;
126 default-state = "keep";
127 };
128
129 led@2 {
130 reg = <2>;
131 color = <LED_COLOR_ID_GREEN>;
132 function = LED_FUNCTION_LAN;
133 default-state = "keep";
134 };
135 };
136 };
137 };
138 };
139
140 &i2c1 {
141 clock-frequency = <100000>;
142 pinctrl-names = "default", "gpio";
143 pinctrl-0 = <&pinctrl_i2c1>;
144 pinctrl-1 = <&pinctrl_i2c1_gpio>;
145 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
146 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
147 status = "okay";
148
149 gsc: gsc@20 {
150 compatible = "gw,gsc";
151 reg = <0x20>;
152 pinctrl-0 = <&pinctrl_gsc>;
153 interrupt-parent = <&gpio2>;
154 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
155 interrupt-controller;
156 #interrupt-cells = <1>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 adc {
161 compatible = "gw,gsc-adc";
162 #address-cells = <1>;
163 #size-cells = <0>;
164
165 channel@6 {
166 gw,mode = <0>;
167 reg = <0x06>;
168 label = "temp";
169 };
170
171 channel@8 {
172 gw,mode = <3>;
173 reg = <0x08>;
174 label = "vdd_bat";
175 };
176
177 channel@16 {
178 gw,mode = <4>;
179 reg = <0x16>;
180 label = "fan_tach";
181 };
182
183 channel@82 {
184 gw,mode = <2>;
185 reg = <0x82>;
186 label = "vdd_vin";
187 gw,voltage-divider-ohms = <22100 1000>;
188 };
189
190 channel@84 {
191 gw,mode = <2>;
192 reg = <0x84>;
193 label = "vdd_adc1";
194 gw,voltage-divider-ohms = <10000 10000>;
195 };
196
197 channel@86 {
198 gw,mode = <2>;
199 reg = <0x86>;
200 label = "vdd_adc2";
201 gw,voltage-divider-ohms = <10000 10000>;
202 };
203
204 channel@88 {
205 gw,mode = <2>;
206 reg = <0x88>;
207 label = "vdd_dram";
208 };
209
210 channel@8c {
211 gw,mode = <2>;
212 reg = <0x8c>;
213 label = "vdd_1p2";
214 };
215
216 channel@8e {
217 gw,mode = <2>;
218 reg = <0x8e>;
219 label = "vdd_1p0";
220 };
221
222 channel@90 {
223 gw,mode = <2>;
224 reg = <0x90>;
225 label = "vdd_2p5";
226 gw,voltage-divider-ohms = <10000 10000>;
227 };
228
229 channel@92 {
230 gw,mode = <2>;
231 reg = <0x92>;
232 label = "vdd_3p3";
233 gw,voltage-divider-ohms = <10000 10000>;
234 };
235
236 channel@98 {
237 gw,mode = <2>;
238 reg = <0x98>;
239 label = "vdd_0p95";
240 };
241
242 channel@9a {
243 gw,mode = <2>;
244 reg = <0x9a>;
245 label = "vdd_1p8";
246 };
247
248 channel@a2 {
249 gw,mode = <2>;
250 reg = <0xa2>;
251 label = "vdd_gsc";
252 gw,voltage-divider-ohms = <10000 10000>;
253 };
254 };
255
256 fan-controller@0 {
257 compatible = "gw,gsc-fan";
258 reg = <0x0a>;
259 };
260 };
261
262 gpio: gpio@23 {
263 compatible = "nxp,pca9555";
264 reg = <0x23>;
265 gpio-controller;
266 #gpio-cells = <2>;
267 interrupt-parent = <&gsc>;
268 interrupts = <4>;
269 };
270
271 eeprom@50 {
272 compatible = "atmel,24c02";
273 reg = <0x50>;
274 pagesize = <16>;
275 };
276
277 eeprom@51 {
278 compatible = "atmel,24c02";
279 reg = <0x51>;
280 pagesize = <16>;
281 };
282
283 eeprom@52 {
284 compatible = "atmel,24c02";
285 reg = <0x52>;
286 pagesize = <16>;
287 };
288
289 eeprom@53 {
290 compatible = "atmel,24c02";
291 reg = <0x53>;
292 pagesize = <16>;
293 };
294
295 rtc@68 {
296 compatible = "dallas,ds1672";
297 reg = <0x68>;
298 };
299
300 pmic@69 {
301 compatible = "mps,mp5416";
302 reg = <0x69>;
303
304 regulators {
305 /* vdd_0p95: DRAM/GPU/VPU */
306 buck1 {
307 regulator-name = "buck1";
308 regulator-min-microvolt = <800000>;
309 regulator-max-microvolt = <1000000>;
310 regulator-min-microamp = <3800000>;
311 regulator-max-microamp = <6800000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
315
316 /* vdd_soc */
317 buck2 {
318 regulator-name = "buck2";
319 regulator-min-microvolt = <800000>;
320 regulator-max-microvolt = <900000>;
321 regulator-min-microamp = <2200000>;
322 regulator-max-microamp = <5200000>;
323 regulator-boot-on;
324 regulator-always-on;
325 };
326
327 /* vdd_arm */
328 buck3_reg: buck3 {
329 regulator-name = "buck3";
330 regulator-min-microvolt = <800000>;
331 regulator-max-microvolt = <1000000>;
332 regulator-min-microamp = <3800000>;
333 regulator-max-microamp = <6800000>;
334 regulator-always-on;
335 };
336
337 /* vdd_1p8 */
338 buck4 {
339 regulator-name = "buck4";
340 regulator-min-microvolt = <1800000>;
341 regulator-max-microvolt = <1800000>;
342 regulator-min-microamp = <2200000>;
343 regulator-max-microamp = <5200000>;
344 regulator-boot-on;
345 regulator-always-on;
346 };
347
348 /* nvcc_snvs_1p8 */
349 ldo1 {
350 regulator-name = "ldo1";
351 regulator-min-microvolt = <1800000>;
352 regulator-max-microvolt = <1800000>;
353 regulator-boot-on;
354 regulator-always-on;
355 };
356
357 /* vdd_snvs_0p8 */
358 ldo2 {
359 regulator-name = "ldo2";
360 regulator-min-microvolt = <800000>;
361 regulator-max-microvolt = <800000>;
362 regulator-boot-on;
363 regulator-always-on;
364 };
365
366 /* vdd_0p9 */
367 ldo3 {
368 regulator-name = "ldo3";
369 regulator-min-microvolt = <900000>;
370 regulator-max-microvolt = <900000>;
371 regulator-boot-on;
372 regulator-always-on;
373 };
374
375 /* vdd_1p8 */
376 ldo4 {
377 regulator-name = "ldo4";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 regulator-boot-on;
381 regulator-always-on;
382 };
383 };
384 };
385 };
386
387 &i2c2 {
388 clock-frequency = <400000>;
389 pinctrl-names = "default", "gpio";
390 pinctrl-0 = <&pinctrl_i2c2>;
391 pinctrl-1 = <&pinctrl_i2c2_gpio>;
392 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
393 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
394 status = "okay";
395
396 eeprom@52 {
397 compatible = "atmel,24c32";
398 reg = <0x52>;
399 pagesize = <32>;
400 };
401 };
402
403 /* console */
404 &uart2 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_uart2>;
407 status = "okay";
408 };
409
410 /* eMMC */
411 &usdhc3 {
412 pinctrl-names = "default", "state_100mhz", "state_200mhz";
413 pinctrl-0 = <&pinctrl_usdhc3>;
414 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
415 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
416 bus-width = <8>;
417 non-removable;
418 status = "okay";
419 };
420
421 &wdog1 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_wdog>;
424 fsl,ext-reset-output;
425 status = "okay";
426 };
427
428 &iomuxc {
429 pinctrl_fec1: fec1grp {
430 fsl,pins = <
431 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
432 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
433 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
434 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
435 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
436 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
437 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
438 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
439 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
440 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
441 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
442 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
443 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
444 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
445 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
446 >;
447 };
448
449 pinctrl_gsc: gscgrp {
450 fsl,pins = <
451 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
452 >;
453 };
454
455 pinctrl_i2c1: i2c1grp {
456 fsl,pins = <
457 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
458 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
459 >;
460 };
461
462 pinctrl_i2c1_gpio: i2c1gpiogrp {
463 fsl,pins = <
464 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
465 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
466 >;
467 };
468
469 pinctrl_i2c2: i2c2grp {
470 fsl,pins = <
471 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
472 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
473 >;
474 };
475
476 pinctrl_i2c2_gpio: i2c2gpiogrp {
477 fsl,pins = <
478 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
479 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
480 >;
481 };
482
483 pinctrl_uart2: uart2grp {
484 fsl,pins = <
485 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
486 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
487 >;
488 };
489
490 pinctrl_usdhc3: usdhc3grp {
491 fsl,pins = <
492 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
493 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
494 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
495 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
496 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
497 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
498 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
499 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
500 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
501 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
502 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
503 >;
504 };
505
506 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
507 fsl,pins = <
508 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
509 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
510 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
511 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
512 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
513 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
514 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
515 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
516 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
517 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
518 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
519 >;
520 };
521
522 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
523 fsl,pins = <
524 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
525 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
526 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
527 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
528 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
529 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
530 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
531 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
532 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
533 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
534 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
535 >;
536 };
537
538 pinctrl_wdog: wdoggrp {
539 fsl,pins = <
540 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
541 >;
542 };
543 };
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