1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12
13 #include "imx8mm.dtsi"
14
15 / {
16 model = "Gateworks Venice GW7903 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
18
19 aliases {
20 ethernet0 = &fec1;
21 usb0 = &usbotg1;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35
36 key-user-pb {
37 label = "user_pb";
38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
39 linux,code = <BTN_0>;
40 };
41
42 key-user-pb1x {
43 label = "user_pb1x";
44 linux,code = <BTN_1>;
45 interrupt-parent = <&gsc>;
46 interrupts = <0>;
47 };
48
49 key-erased {
50 label = "key_erased";
51 linux,code = <BTN_2>;
52 interrupt-parent = <&gsc>;
53 interrupts = <1>;
54 };
55
56 key-eeprom-wp {
57 label = "eeprom_wp";
58 linux,code = <BTN_3>;
59 interrupt-parent = <&gsc>;
60 interrupts = <2>;
61 };
62
63 switch-hold {
64 label = "switch_hold";
65 linux,code = <BTN_5>;
66 interrupt-parent = <&gsc>;
67 interrupts = <7>;
68 };
69 };
70
71 led-controller {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
75
76 led-0 {
77 function = LED_FUNCTION_STATUS;
78 color = <LED_COLOR_ID_RED>;
79 label = "led01_red";
80 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led-1 {
85 function = LED_FUNCTION_STATUS;
86 color = <LED_COLOR_ID_GREEN>;
87 label = "led01_grn";
88 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
89 default-state = "off";
90 };
91
92 led-2 {
93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_RED>;
95 label = "led02_red";
96 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
97 default-state = "off";
98 };
99
100 led-3 {
101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_GREEN>;
103 label = "led02_grn";
104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
105 default-state = "off";
106 };
107
108 led-4 {
109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_RED>;
111 label = "led03_red";
112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
113 default-state = "off";
114 };
115
116 led-5 {
117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_GREEN>;
119 label = "led03_grn";
120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
121 default-state = "off";
122 };
123
124 led-6 {
125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_RED>;
127 label = "led04_red";
128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
129 default-state = "off";
130 };
131
132 led-7 {
133 function = LED_FUNCTION_STATUS;
134 color = <LED_COLOR_ID_GREEN>;
135 label = "led04_grn";
136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
137 default-state = "off";
138 };
139
140 led-8 {
141 function = LED_FUNCTION_STATUS;
142 color = <LED_COLOR_ID_RED>;
143 label = "led05_red";
144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
145 default-state = "off";
146 };
147
148 led-9 {
149 function = LED_FUNCTION_STATUS;
150 color = <LED_COLOR_ID_GREEN>;
151 label = "led05_grn";
152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
153 default-state = "off";
154 };
155
156 led-a {
157 function = LED_FUNCTION_STATUS;
158 color = <LED_COLOR_ID_RED>;
159 label = "led06_red";
160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161 default-state = "off";
162 };
163
164 led-b {
165 function = LED_FUNCTION_STATUS;
166 color = <LED_COLOR_ID_GREEN>;
167 label = "led06_grn";
168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
169 default-state = "off";
170 };
171 };
172
173 pcie0_refclk: pcie0-refclk {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <100000000>;
177 };
178
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed";
181 regulator-name = "3P3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 };
186 };
187
188 &A53_0 {
189 cpu-supply = <&buck2>;
190 };
191
192 &A53_1 {
193 cpu-supply = <&buck2>;
194 };
195
196 &A53_2 {
197 cpu-supply = <&buck2>;
198 };
199
200 &A53_3 {
201 cpu-supply = <&buck2>;
202 };
203
204 &ddrc {
205 operating-points-v2 = <&ddrc_opp_table>;
206
207 ddrc_opp_table: opp-table {
208 compatible = "operating-points-v2";
209
210 opp-25000000 {
211 opp-hz = /bits/ 64 <25000000>;
212 };
213
214 opp-100000000 {
215 opp-hz = /bits/ 64 <100000000>;
216 };
217
218 opp-750000000 {
219 opp-hz = /bits/ 64 <750000000>;
220 };
221 };
222 };
223
224 &fec1 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_fec1>;
227 phy-mode = "rgmii-id";
228 phy-handle = <ðphy0>;
229 local-mac-address = [00 00 00 00 00 00];
230 status = "okay";
231
232 mdio {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 ethphy0: ethernet-phy@0 {
237 compatible = "ethernet-phy-ieee802.3-c22";
238 reg = <0>;
239 rx-internal-delay-ps = <2000>;
240 tx-internal-delay-ps = <2500>;
241 };
242 };
243 };
244
245 &gpio1 {
246 gpio-line-names = "", "", "", "", "", "", "", "",
247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
248 "", "", "", "", "", "", "", "",
249 "", "", "", "", "", "", "", "";
250 };
251
252 &gpio2 {
253 gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
254 "dig1_out#", "dig1_in", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "";
257 };
258
259 &gpio5 {
260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
262 "", "", "", "", "", "", "", "",
263 "", "", "", "", "", "", "", "";
264 };
265
266 &i2c1 {
267 clock-frequency = <100000>;
268 pinctrl-names = "default", "gpio";
269 pinctrl-0 = <&pinctrl_i2c1>;
270 pinctrl-1 = <&pinctrl_i2c1_gpio>;
271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
273 status = "okay";
274
275 gsc: gsc@20 {
276 compatible = "gw,gsc";
277 reg = <0x20>;
278 pinctrl-0 = <&pinctrl_gsc>;
279 interrupt-parent = <&gpio4>;
280 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
281 interrupt-controller;
282 #interrupt-cells = <1>;
283 #address-cells = <1>;
284 #size-cells = <0>;
285
286 adc {
287 compatible = "gw,gsc-adc";
288 #address-cells = <1>;
289 #size-cells = <0>;
290
291 channel@6 {
292 gw,mode = <0>;
293 reg = <0x06>;
294 label = "temp";
295 };
296
297 channel@8 {
298 gw,mode = <3>;
299 reg = <0x08>;
300 label = "vdd_bat";
301 };
302
303 channel@82 {
304 gw,mode = <2>;
305 reg = <0x82>;
306 label = "vin";
307 gw,voltage-divider-ohms = <22100 1000>;
308 gw,voltage-offset-microvolt = <700000>;
309 };
310
311 channel@84 {
312 gw,mode = <2>;
313 reg = <0x84>;
314 label = "vdd_5p0";
315 gw,voltage-divider-ohms = <10000 10000>;
316 };
317
318 channel@86 {
319 gw,mode = <2>;
320 reg = <0x86>;
321 label = "vdd_3p3";
322 gw,voltage-divider-ohms = <10000 10000>;
323 };
324
325 channel@88 {
326 gw,mode = <2>;
327 reg = <0x88>;
328 label = "vdd_0p9";
329 };
330
331 channel@8c {
332 gw,mode = <2>;
333 reg = <0x8c>;
334 label = "vdd_soc";
335 };
336
337 channel@8e {
338 gw,mode = <2>;
339 reg = <0x8e>;
340 label = "vdd_arm";
341 };
342
343 channel@90 {
344 gw,mode = <2>;
345 reg = <0x90>;
346 label = "vdd_1p8";
347 };
348
349 channel@92 {
350 gw,mode = <2>;
351 reg = <0x92>;
352 label = "vdd_dram";
353 };
354
355 channel@a2 {
356 gw,mode = <2>;
357 reg = <0xa2>;
358 label = "vdd_gsc";
359 gw,voltage-divider-ohms = <10000 10000>;
360 };
361 };
362 };
363
364 gpio: gpio@23 {
365 compatible = "nxp,pca9555";
366 reg = <0x23>;
367 gpio-controller;
368 #gpio-cells = <2>;
369 interrupt-parent = <&gsc>;
370 interrupts = <4>;
371 };
372
373 eeprom@50 {
374 compatible = "atmel,24c02";
375 reg = <0x50>;
376 pagesize = <16>;
377 };
378
379 eeprom@51 {
380 compatible = "atmel,24c02";
381 reg = <0x51>;
382 pagesize = <16>;
383 };
384
385 eeprom@52 {
386 compatible = "atmel,24c02";
387 reg = <0x52>;
388 pagesize = <16>;
389 };
390
391 eeprom@53 {
392 compatible = "atmel,24c02";
393 reg = <0x53>;
394 pagesize = <16>;
395 };
396
397 rtc@68 {
398 compatible = "dallas,ds1672";
399 reg = <0x68>;
400 };
401 };
402
403 &i2c2 {
404 clock-frequency = <400000>;
405 pinctrl-names = "default", "gpio";
406 pinctrl-0 = <&pinctrl_i2c2>;
407 pinctrl-1 = <&pinctrl_i2c2_gpio>;
408 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
409 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
410 status = "okay";
411
412 pmic@4b {
413 compatible = "rohm,bd71847";
414 reg = <0x4b>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pmic>;
417 interrupt-parent = <&gpio3>;
418 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
419 rohm,reset-snvs-powered;
420 #clock-cells = <0>;
421 clocks = <&osc_32k>;
422 clock-output-names = "clk-32k-out";
423
424 regulators {
425 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
426 BUCK1 {
427 regulator-name = "buck1";
428 regulator-min-microvolt = <700000>;
429 regulator-max-microvolt = <1300000>;
430 regulator-boot-on;
431 regulator-always-on;
432 regulator-ramp-delay = <1250>;
433 };
434
435 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
436 buck2: BUCK2 {
437 regulator-name = "buck2";
438 regulator-min-microvolt = <700000>;
439 regulator-max-microvolt = <1300000>;
440 regulator-boot-on;
441 regulator-always-on;
442 regulator-ramp-delay = <1250>;
443 rohm,dvs-run-voltage = <1000000>;
444 rohm,dvs-idle-voltage = <900000>;
445 };
446
447 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
448 BUCK3 {
449 regulator-name = "buck3";
450 regulator-min-microvolt = <700000>;
451 regulator-max-microvolt = <1350000>;
452 regulator-boot-on;
453 regulator-always-on;
454 };
455
456 /* vdd_3p3 */
457 BUCK4 {
458 regulator-name = "buck4";
459 regulator-min-microvolt = <3000000>;
460 regulator-max-microvolt = <3300000>;
461 regulator-boot-on;
462 regulator-always-on;
463 };
464
465 /* vdd_1p8 */
466 BUCK5 {
467 regulator-name = "buck5";
468 regulator-min-microvolt = <1605000>;
469 regulator-max-microvolt = <1995000>;
470 regulator-boot-on;
471 regulator-always-on;
472 };
473
474 /* vdd_dram */
475 BUCK6 {
476 regulator-name = "buck6";
477 regulator-min-microvolt = <800000>;
478 regulator-max-microvolt = <1400000>;
479 regulator-boot-on;
480 regulator-always-on;
481 };
482
483 /* nvcc_snvs_1p8 */
484 LDO1 {
485 regulator-name = "ldo1";
486 regulator-min-microvolt = <1600000>;
487 regulator-max-microvolt = <1900000>;
488 regulator-boot-on;
489 regulator-always-on;
490 };
491
492 /* vdd_snvs_0p8 */
493 LDO2 {
494 regulator-name = "ldo2";
495 regulator-min-microvolt = <800000>;
496 regulator-max-microvolt = <900000>;
497 regulator-boot-on;
498 regulator-always-on;
499 };
500
501 /* vdda_1p8 */
502 LDO3 {
503 regulator-name = "ldo3";
504 regulator-min-microvolt = <1800000>;
505 regulator-max-microvolt = <3300000>;
506 regulator-boot-on;
507 regulator-always-on;
508 };
509
510 LDO4 {
511 regulator-name = "ldo4";
512 regulator-min-microvolt = <900000>;
513 regulator-max-microvolt = <1800000>;
514 regulator-boot-on;
515 regulator-always-on;
516 };
517
518 LDO6 {
519 regulator-name = "ldo6";
520 regulator-min-microvolt = <900000>;
521 regulator-max-microvolt = <1800000>;
522 regulator-boot-on;
523 regulator-always-on;
524 };
525 };
526 };
527 };
528
529 &i2c3 {
530 clock-frequency = <400000>;
531 pinctrl-names = "default", "gpio";
532 pinctrl-0 = <&pinctrl_i2c3>;
533 pinctrl-1 = <&pinctrl_i2c3_gpio>;
534 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
535 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
536 status = "okay";
537
538 accelerometer@19 {
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_accel>;
541 compatible = "st,lis2de12";
542 reg = <0x19>;
543 st,drdy-int-pin = <1>;
544 interrupt-parent = <&gpio1>;
545 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
546 };
547 };
548
549 &pcie_phy {
550 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
551 fsl,clkreq-unsupported;
552 clocks = <&pcie0_refclk>;
553 clock-names = "ref";
554 status = "okay";
555 };
556
557 &pcie0 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_pcie0>;
560 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
561 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
562 <&clk IMX8MM_CLK_PCIE1_AUX>;
563 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
564 <&clk IMX8MM_CLK_PCIE1_CTRL>;
565 assigned-clock-rates = <10000000>, <250000000>;
566 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
567 <&clk IMX8MM_SYS_PLL2_250M>;
568 status = "okay";
569 };
570
571 &disp_blk_ctrl {
572 status = "disabled";
573 };
574
575 &pgc_mipi {
576 status = "disabled";
577 };
578
579 /* off-board RS232/RS485/RS422 */
580 &uart1 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart1>;
583 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
584 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
585 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
586 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
587 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
588 status = "okay";
589 };
590
591 /* console */
592 &uart2 {
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_uart2>;
595 status = "okay";
596 };
597
598 &usbotg1 {
599 dr_mode = "host";
600 disable-over-current;
601 status = "okay";
602 };
603
604 /* microSD */
605 &usdhc2 {
606 pinctrl-names = "default", "state_100mhz", "state_200mhz";
607 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
608 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
611 bus-width = <4>;
612 vmmc-supply = <®_3p3v>;
613 status = "okay";
614 };
615
616 /* eMMC */
617 &usdhc3 {
618 pinctrl-names = "default", "state_100mhz", "state_200mhz";
619 pinctrl-0 = <&pinctrl_usdhc3>;
620 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
621 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
622 bus-width = <8>;
623 non-removable;
624 status = "okay";
625 };
626
627 &wdog1 {
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_wdog>;
630 fsl,ext-reset-output;
631 status = "okay";
632 };
633
634 &iomuxc {
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_hog>;
637
638 pinctrl_hog: hoggrp {
639 fsl,pins = <
640 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
641 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
642 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
643 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
644 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
645 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
646 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
647 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
648 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
649 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
650 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
651 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
652 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
653 >;
654 };
655
656 pinctrl_accel: accelgrp {
657 fsl,pins = <
658 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
659 >;
660 };
661
662 pinctrl_fec1: fec1grp {
663 fsl,pins = <
664 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
665 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
666 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
667 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
668 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
669 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
670 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
671 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
672 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
673 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
674 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
675 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
676 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
677 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
678 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
679 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
680 >;
681 };
682
683 pinctrl_gsc: gscgrp {
684 fsl,pins = <
685 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
686 >;
687 };
688
689 pinctrl_i2c1: i2c1grp {
690 fsl,pins = <
691 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
692 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
693 >;
694 };
695
696 pinctrl_i2c1_gpio: i2c1gpiogrp {
697 fsl,pins = <
698 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
699 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
700 >;
701 };
702
703 pinctrl_i2c2: i2c2grp {
704 fsl,pins = <
705 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
706 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
707 >;
708 };
709
710 pinctrl_i2c2_gpio: i2c2gpiogrp {
711 fsl,pins = <
712 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
713 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
714 >;
715 };
716
717 pinctrl_i2c3: i2c3grp {
718 fsl,pins = <
719 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
720 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
721 >;
722 };
723
724 pinctrl_i2c3_gpio: i2c3gpiogrp {
725 fsl,pins = <
726 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
727 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
728 >;
729 };
730
731 pinctrl_gpio_leds: gpioledgrp {
732 fsl,pins = <
733 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
734 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
735 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
736 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
737 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
738 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
739 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
740 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
741 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
742 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
743 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
744 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
745 >;
746 };
747
748 pinctrl_pcie0: pciegrp {
749 fsl,pins = <
750 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
751 >;
752 };
753
754 pinctrl_pmic: pmicgrp {
755 fsl,pins = <
756 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
757 >;
758 };
759
760 pinctrl_uart1: uart1grp {
761 fsl,pins = <
762 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
763 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
764 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
765 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
766 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
767 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
768 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
769 >;
770 };
771
772 pinctrl_uart2: uart2grp {
773 fsl,pins = <
774 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
775 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
776 >;
777 };
778
779 pinctrl_usdhc2: usdhc2grp {
780 fsl,pins = <
781 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
782 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
783 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
784 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
785 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
786 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
787 >;
788 };
789
790 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
791 fsl,pins = <
792 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
793 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
794 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
795 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
796 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
797 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
798 >;
799 };
800
801 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
802 fsl,pins = <
803 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
804 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
805 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
806 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
807 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
808 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
809 >;
810 };
811
812 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
813 fsl,pins = <
814 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
815 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >;
817 };
818
819 pinctrl_usdhc3: usdhc3grp {
820 fsl,pins = <
821 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
822 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
823 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
824 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
825 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
826 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
827 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
828 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
829 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
830 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
831 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
832 >;
833 };
834
835 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
836 fsl,pins = <
837 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
838 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
839 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
840 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
841 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
842 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
843 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
844 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
845 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
846 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
847 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
848 >;
849 };
850
851 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
852 fsl,pins = <
853 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
854 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
855 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
856 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
857 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
858 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
859 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
860 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
861 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
862 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
863 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
864 >;
865 };
866
867 pinctrl_wdog: wdoggrp {
868 fsl,pins = <
869 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
870 >;
871 };
872 };
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