1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <dt-bindings/usb/pd.h>
7 #include "imx8mn.dtsi"
8
9 / {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 hdmi-connector {
27 compatible = "hdmi-connector";
28 label = "hdmi";
29 type = "a";
30
31 port {
32 hdmi_connector_in: endpoint {
33 remote-endpoint = <&adv7535_out>;
34 };
35 };
36 };
37
38 memory@40000000 {
39 device_type = "memory";
40 reg = <0x0 0x40000000 0 0x80000000>;
41 };
42
43 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>;
52 enable-active-high;
53 };
54
55 reg_1v5: regulator-1v5 {
56 compatible = "regulator-fixed";
57 regulator-name = "VDD_1V5";
58 regulator-min-microvolt = <1500000>;
59 regulator-max-microvolt = <1500000>;
60 };
61
62 reg_1v8: regulator-1v8 {
63 compatible = "regulator-fixed";
64 regulator-name = "VDD_1V8";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
67 };
68
69 reg_vddext_3v3: regulator-vddext-3v3 {
70 compatible = "regulator-fixed";
71 regulator-name = "VDDEXT_3V3";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 };
75
76 ir-receiver {
77 compatible = "gpio-ir-receiver";
78 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ir>;
81 linux,autosuspend-period = <125>;
82 };
83
84 audio_codec_bt_sco: audio-codec-bt-sco {
85 compatible = "linux,bt-sco";
86 #sound-dai-cells = <1>;
87 };
88
89 wm8524: audio-codec {
90 #sound-dai-cells = <0>;
91 compatible = "wlf,wm8524";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio_wlf>;
94 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
95 };
96
97 sound-bt-sco {
98 compatible = "simple-audio-card";
99 simple-audio-card,name = "bt-sco-audio";
100 simple-audio-card,format = "dsp_a";
101 simple-audio-card,bitclock-inversion;
102 simple-audio-card,frame-master = <&btcpu>;
103 simple-audio-card,bitclock-master = <&btcpu>;
104
105 btcpu: simple-audio-card,cpu {
106 sound-dai = <&sai2>;
107 dai-tdm-slot-num = <2>;
108 dai-tdm-slot-width = <16>;
109 };
110
111 simple-audio-card,codec {
112 sound-dai = <&audio_codec_bt_sco 1>;
113 };
114 };
115
116 sound-wm8524 {
117 compatible = "fsl,imx-audio-wm8524";
118 model = "wm8524-audio";
119 audio-cpu = <&sai3>;
120 audio-codec = <&wm8524>;
121 audio-asrc = <&easrc>;
122 audio-routing =
123 "Line Out Jack", "LINEVOUTL",
124 "Line Out Jack", "LINEVOUTR";
125 };
126
127 spdif_out: spdif-out {
128 compatible = "linux,spdif-dit";
129 #sound-dai-cells = <0>;
130 };
131
132 spdif_in: spdif-in {
133 compatible = "linux,spdif-dir";
134 #sound-dai-cells = <0>;
135 };
136
137 sound-spdif {
138 compatible = "fsl,imx-audio-spdif";
139 model = "imx-spdif";
140 audio-cpu = <&spdif1>;
141 audio-codec = <&spdif_out>, <&spdif_in>;
142 };
143
144 sound-micfil {
145 compatible = "fsl,imx-audio-card";
146 model = "micfil-audio";
147
148 pri-dai-link {
149 link-name = "micfil hifi";
150 format = "i2s";
151
152 cpu {
153 sound-dai = <&micfil>;
154 };
155 };
156 };
157 };
158
159 &easrc {
160 fsl,asrc-rate = <48000>;
161 status = "okay";
162 };
163
164 &fec1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>;
169 fsl,magic-packet;
170 status = "okay";
171
172 mdio {
173 #address-cells = <1>;
174 #size-cells = <0>;
175
176 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>;
179 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <10000>;
181 qca,disable-smarteee;
182 vddio-supply = <&vddio>;
183
184 vddio: vddio-regulator {
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 };
188 };
189 };
190 };
191
192 &flexspi {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexspi>;
195 status = "okay";
196
197 flash0: flash@0 {
198 compatible = "jedec,spi-nor";
199 reg = <0>;
200 #address-cells = <1>;
201 #size-cells = <1>;
202 spi-max-frequency = <166000000>;
203 spi-tx-bus-width = <4>;
204 spi-rx-bus-width = <4>;
205 };
206 };
207
208 &i2c1 {
209 clock-frequency = <400000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay";
213 };
214
215 &i2c2 {
216 clock-frequency = <400000>;
217 pinctrl-names = "default", "gpio";
218 pinctrl-0 = <&pinctrl_i2c2>;
219 pinctrl-1 = <&pinctrl_i2c2_gpio>;
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
222 status = "okay";
223
224 hdmi@3d {
225 compatible = "adi,adv7535";
226 reg = <0x3d>;
227 interrupt-parent = <&gpio1>;
228 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
229 adi,dsi-lanes = <4>;
230 v3p3-supply = <®_vddext_3v3>;
231
232 ports {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 port@0 {
237 reg = <0>;
238
239 adv7535_in: endpoint {
240 remote-endpoint = <&dsi_out>;
241 };
242 };
243
244 port@1 {
245 reg = <1>;
246
247 adv7535_out: endpoint {
248 remote-endpoint = <&hdmi_connector_in>;
249 };
250 };
251
252 };
253 };
254
255 ptn5110: tcpc@50 {
256 compatible = "nxp,ptn5110", "tcpci";
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_typec1>;
259 reg = <0x50>;
260 interrupt-parent = <&gpio2>;
261 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
262 status = "okay";
263
264 typec1_con: connector {
265 compatible = "usb-c-connector";
266 label = "USB-C";
267 power-role = "dual";
268 data-role = "dual";
269 try-power-role = "sink";
270 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <15000000>;
274 self-powered;
275
276 port {
277 typec1_dr_sw: endpoint {
278 remote-endpoint = <&usb1_drd_sw>;
279 };
280 };
281 };
282 };
283 };
284
285 &i2c3 {
286 clock-frequency = <400000>;
287 pinctrl-names = "default", "gpio";
288 pinctrl-0 = <&pinctrl_i2c3>;
289 pinctrl-1 = <&pinctrl_i2c3_gpio>;
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
292 status = "okay";
293
294 pca6416: gpio@20 {
295 compatible = "ti,tca6416";
296 reg = <0x20>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 };
300
301 camera@3c {
302 compatible = "ovti,ov5640";
303 reg = <0x3c>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_camera>;
306 clocks = <&clk IMX8MN_CLK_CLKO1>;
307 clock-names = "xclk";
308 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
309 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
310 assigned-clock-rates = <24000000>;
311 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
312 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
313 AVDD-supply = <®_1v8>;
314 DVDD-supply = <®_1v5>;
315
316 port {
317 ov5640_to_mipi_csi2: endpoint {
318 remote-endpoint = <&imx8mn_mipi_csi_in>;
319 clock-lanes = <0>;
320 data-lanes = <1 2>;
321 };
322 };
323 };
324 };
325
326 &isi {
327 status = "okay";
328 };
329
330 &micfil {
331 #sound-dai-cells = <0>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_pdm>;
334 assigned-clocks = <&clk IMX8MN_CLK_PDM>;
335 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
336 assigned-clock-rates = <196608000>;
337 status = "okay";
338 };
339
340 &mipi_csi {
341 status = "okay";
342
343 ports {
344 port@0 {
345 imx8mn_mipi_csi_in: endpoint {
346 remote-endpoint = <&ov5640_to_mipi_csi2>;
347 data-lanes = <1 2>;
348 };
349 };
350 };
351 };
352
353 &lcdif {
354 status = "okay";
355 };
356
357 &mipi_dsi {
358 samsung,esc-clock-frequency = <10000000>;
359 status = "okay";
360
361 ports {
362 port@1 {
363 reg = <1>;
364
365 dsi_out: endpoint {
366 remote-endpoint = <&adv7535_in>;
367 data-lanes = <1 2 3 4>;
368 };
369 };
370 };
371 };
372
373 &sai2 {
374 #sound-dai-cells = <0>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_sai2>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>;
380 status = "okay";
381 };
382
383 &sai3 {
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_sai3>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>;
389 fsl,sai-mclk-direction-output;
390 status = "okay";
391 };
392
393 &snvs_pwrkey {
394 status = "okay";
395 };
396
397 &spdif1 {
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_spdif1>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>;
403 status = "okay";
404 };
405
406 &uart1 { /* BT */
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart1>;
409 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
410 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
411 uart-has-rtscts;
412 status = "okay";
413 };
414
415 &uart2 { /* console */
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay";
419 };
420
421 &uart3 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart3>;
424 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
426 uart-has-rtscts;
427 status = "okay";
428 };
429
430 &usbphynop1 {
431 wakeup-source;
432 };
433
434 &usbotg1 {
435 dr_mode = "otg";
436 hnp-disable;
437 srp-disable;
438 adp-disable;
439 usb-role-switch;
440 disable-over-current;
441 samsung,picophy-pre-emp-curr-control = <3>;
442 samsung,picophy-dc-vol-level-adjust = <7>;
443 status = "okay";
444
445 port {
446 usb1_drd_sw: endpoint {
447 remote-endpoint = <&typec1_dr_sw>;
448 };
449 };
450 };
451
452 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay";
463 };
464
465 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>;
473 non-removable;
474 status = "okay";
475 };
476
477 &wdog1 {
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output;
481 status = "okay";
482 };
483
484 &iomuxc {
485 pinctrl_camera: cameragrp {
486 fsl,pins = <
487 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
488 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
489 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
490 >;
491 };
492
493 pinctrl_fec1: fec1grp {
494 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >;
511 };
512
513 pinctrl_flexspi: flexspigrp {
514 fsl,pins = <
515 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
516 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
517 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
518 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
519 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
520 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
521 >;
522 };
523
524 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >;
528 };
529
530 pinctrl_gpio_wlf: gpiowlfgrp {
531 fsl,pins = <
532 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
533 >;
534 };
535
536 pinctrl_ir: irgrp {
537 fsl,pins = <
538 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
539 >;
540 };
541
542 pinctrl_i2c1: i2c1grp {
543 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >;
547 };
548
549 pinctrl_i2c2: i2c2grp {
550 fsl,pins = <
551 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
552 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
553 >;
554 };
555
556 pinctrl_i2c2_gpio: i2c2gpiogrp {
557 fsl,pins = <
558 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
559 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
560 >;
561 };
562
563 pinctrl_i2c3: i2c3grp {
564 fsl,pins = <
565 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
566 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
567 >;
568 };
569
570 pinctrl_i2c3_gpio: i2c3gpiogrp {
571 fsl,pins = <
572 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
573 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
574 >;
575 };
576
577 pinctrl_pdm: pdmgrp {
578 fsl,pins = <
579 MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
580 MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
581 MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
582 MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
583 MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6
584 MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6
585 MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6
586 >;
587 };
588
589 pinctrl_pmic: pmicirqgrp {
590 fsl,pins = <
591 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
592 >;
593 };
594
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
596 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >;
599 };
600
601 pinctrl_sai2: sai2grp {
602 fsl,pins = <
603 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
604 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
605 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
606 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
607 >;
608 };
609
610 pinctrl_sai3: sai3grp {
611 fsl,pins = <
612 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
613 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
614 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
615 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
616 >;
617 };
618
619 pinctrl_spdif1: spdif1grp {
620 fsl,pins = <
621 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
622 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
623 >;
624 };
625
626 pinctrl_typec1: typec1grp {
627 fsl,pins = <
628 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
629 >;
630 };
631
632 pinctrl_uart1: uart1grp {
633 fsl,pins = <
634 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
635 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
636 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
637 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
638 >;
639 };
640
641 pinctrl_uart2: uart2grp {
642 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >;
646 };
647
648 pinctrl_uart3: uart3grp {
649 fsl,pins = <
650 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
651 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
652 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
653 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
654 >;
655 };
656
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
658 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >;
661 };
662
663 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >;
673 };
674
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
676 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >;
685 };
686
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
688 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >;
697 };
698
699 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >;
713 };
714
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
716 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >;
729 };
730
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
732 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >;
745 };
746
747 pinctrl_wdog: wdoggrp {
748 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
750 >;
751 };
752 };
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