1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include "imx8mp.dtsi"
10
11 / {
12 model = "NXP i.MX8MPlus EVK board";
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
14
15 chosen {
16 stdout-path = &uart2;
17 };
18
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
21 pwms = <&pwm2 0 100000 0>;
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
25 power-supply = <®_per_12v>;
26 status = "disabled";
27 };
28
29 hdmi-connector {
30 compatible = "hdmi-connector";
31 label = "hdmi";
32 type = "a";
33
34 port {
35 hdmi_connector_in: endpoint {
36 remote-endpoint = <&adv7535_out>;
37 };
38 };
39 };
40
41 gpio-leds {
42 compatible = "gpio-leds";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpio_led>;
45
46 status {
47 label = "yellow:status";
48 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
49 default-state = "on";
50 };
51 };
52
53 memory@40000000 {
54 device_type = "memory";
55 reg = <0x0 0x40000000 0 0xc0000000>,
56 <0x1 0x00000000 0 0xc0000000>;
57 };
58
59 native-hdmi-connector {
60 compatible = "hdmi-connector";
61 label = "HDMI OUT";
62 type = "a";
63
64 port {
65 hdmi_in: endpoint {
66 remote-endpoint = <&hdmi_tx_out>;
67 };
68 };
69 };
70
71 pcie0_refclk: pcie0-refclk {
72 compatible = "fixed-clock";
73 #clock-cells = <0>;
74 clock-frequency = <100000000>;
75 };
76
77 reg_audio_pwr: regulator-audio-pwr {
78 compatible = "regulator-fixed";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_audio_pwr_reg>;
81 regulator-name = "audio-pwr";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 };
87
88 reg_can1_stby: regulator-can1-stby {
89 compatible = "regulator-fixed";
90 regulator-name = "can1-stby";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_flexcan1_reg>;
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
96 enable-active-high;
97 };
98
99 reg_can2_stby: regulator-can2-stby {
100 compatible = "regulator-fixed";
101 regulator-name = "can2-stby";
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_flexcan2_reg>;
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
107 enable-active-high;
108 };
109
110 reg_pcie0: regulator-pcie {
111 compatible = "regulator-fixed";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_pcie0_reg>;
114 regulator-name = "MPCIE_3V3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 };
120
121 reg_per_12v: regulator-per-12v {
122 compatible = "regulator-fixed";
123 regulator-name = "PER_12V";
124 regulator-min-microvolt = <12000000>;
125 regulator-max-microvolt = <12000000>;
126 gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
127 enable-active-high;
128 };
129
130 reg_usdhc2_vmmc: regulator-usdhc2 {
131 compatible = "regulator-fixed";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
134 regulator-name = "VSD_3V3";
135 regulator-min-microvolt = <3300000>;
136 regulator-max-microvolt = <3300000>;
137 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
138 enable-active-high;
139 };
140
141 reg_vext_3v3: regulator-vext-3v3 {
142 compatible = "regulator-fixed";
143 regulator-name = "VEXT_3V3";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 };
147
148 audio_codec_bt_sco: audio-codec-bt-sco {
149 compatible = "linux,bt-sco";
150 #sound-dai-cells = <1>;
151 };
152
153 sound {
154 compatible = "simple-audio-card";
155 simple-audio-card,name = "wm8960-audio";
156 simple-audio-card,format = "i2s";
157 simple-audio-card,frame-master = <&cpudai>;
158 simple-audio-card,bitclock-master = <&cpudai>;
159 simple-audio-card,widgets =
160 "Headphone", "Headphone Jack",
161 "Speaker", "External Speaker",
162 "Microphone", "Mic Jack";
163 simple-audio-card,routing =
164 "Headphone Jack", "HP_L",
165 "Headphone Jack", "HP_R",
166 "External Speaker", "SPK_LP",
167 "External Speaker", "SPK_LN",
168 "External Speaker", "SPK_RP",
169 "External Speaker", "SPK_RN",
170 "LINPUT1", "Mic Jack",
171 "LINPUT3", "Mic Jack",
172 "Mic Jack", "MICB";
173
174 cpudai: simple-audio-card,cpu {
175 sound-dai = <&sai3>;
176 };
177
178 simple-audio-card,codec {
179 sound-dai = <&wm8960>;
180 };
181
182 };
183
184 sound-bt-sco {
185 compatible = "simple-audio-card";
186 simple-audio-card,name = "bt-sco-audio";
187 simple-audio-card,format = "dsp_a";
188 simple-audio-card,bitclock-inversion;
189 simple-audio-card,frame-master = <&btcpu>;
190 simple-audio-card,bitclock-master = <&btcpu>;
191
192 btcpu: simple-audio-card,cpu {
193 sound-dai = <&sai2>;
194 dai-tdm-slot-num = <2>;
195 dai-tdm-slot-width = <16>;
196 };
197
198 simple-audio-card,codec {
199 sound-dai = <&audio_codec_bt_sco 1>;
200 };
201 };
202
203 sound-hdmi {
204 compatible = "fsl,imx-audio-hdmi";
205 model = "audio-hdmi";
206 audio-cpu = <&aud2htx>;
207 hdmi-out;
208 };
209
210 sound-micfil {
211 compatible = "fsl,imx-audio-card";
212 model = "micfil-audio";
213
214 pri-dai-link {
215 link-name = "micfil hifi";
216 format = "i2s";
217
218 cpu {
219 sound-dai = <&micfil>;
220 };
221 };
222 };
223
224 sound-xcvr {
225 compatible = "fsl,imx-audio-card";
226 model = "imx-audio-xcvr";
227
228 pri-dai-link {
229 link-name = "XCVR PCM";
230
231 cpu {
232 sound-dai = <&xcvr>;
233 };
234 };
235 };
236
237 reserved-memory {
238 #address-cells = <2>;
239 #size-cells = <2>;
240 ranges;
241
242 dsp_vdev0vring0: vdev0vring0@942f0000 {
243 reg = <0 0x942f0000 0 0x8000>;
244 no-map;
245 };
246
247 dsp_vdev0vring1: vdev0vring1@942f8000 {
248 reg = <0 0x942f8000 0 0x8000>;
249 no-map;
250 };
251
252 dsp_vdev0buffer: vdev0buffer@94300000 {
253 compatible = "shared-dma-pool";
254 reg = <0 0x94300000 0 0x100000>;
255 no-map;
256 };
257 };
258 };
259
260 &flexspi {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_flexspi0>;
263 status = "okay";
264
265 flash@0 {
266 compatible = "jedec,spi-nor";
267 reg = <0>;
268 spi-max-frequency = <80000000>;
269 spi-tx-bus-width = <1>;
270 spi-rx-bus-width = <4>;
271 };
272 };
273
274 &A53_0 {
275 cpu-supply = <®_arm>;
276 };
277
278 &A53_1 {
279 cpu-supply = <®_arm>;
280 };
281
282 &A53_2 {
283 cpu-supply = <®_arm>;
284 };
285
286 &A53_3 {
287 cpu-supply = <®_arm>;
288 };
289
290 &aud2htx {
291 status = "okay";
292 };
293
294 &eqos {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_eqos>;
297 phy-mode = "rgmii-id";
298 phy-handle = <ðphy0>;
299 snps,force_thresh_dma_mode;
300 snps,mtl-tx-config = <&mtl_tx_setup>;
301 snps,mtl-rx-config = <&mtl_rx_setup>;
302 status = "okay";
303
304 mdio {
305 compatible = "snps,dwmac-mdio";
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 ethphy0: ethernet-phy@1 {
310 compatible = "ethernet-phy-ieee802.3-c22";
311 reg = <1>;
312 eee-broken-1000t;
313 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
314 reset-assert-us = <10000>;
315 reset-deassert-us = <80000>;
316 realtek,clkout-disable;
317 };
318 };
319
320 mtl_tx_setup: tx-queues-config {
321 snps,tx-queues-to-use = <5>;
322
323 queue0 {
324 snps,dcb-algorithm;
325 snps,priority = <0x1>;
326 };
327
328 queue1 {
329 snps,dcb-algorithm;
330 snps,priority = <0x2>;
331 };
332
333 queue2 {
334 snps,dcb-algorithm;
335 snps,priority = <0x4>;
336 };
337
338 queue3 {
339 snps,dcb-algorithm;
340 snps,priority = <0x8>;
341 };
342
343 queue4 {
344 snps,dcb-algorithm;
345 snps,priority = <0xf0>;
346 };
347 };
348
349 mtl_rx_setup: rx-queues-config {
350 snps,rx-queues-to-use = <5>;
351 snps,rx-sched-sp;
352
353 queue0 {
354 snps,dcb-algorithm;
355 snps,priority = <0x1>;
356 snps,map-to-dma-channel = <0>;
357 };
358
359 queue1 {
360 snps,dcb-algorithm;
361 snps,priority = <0x2>;
362 snps,map-to-dma-channel = <1>;
363 };
364
365 queue2 {
366 snps,dcb-algorithm;
367 snps,priority = <0x4>;
368 snps,map-to-dma-channel = <2>;
369 };
370
371 queue3 {
372 snps,dcb-algorithm;
373 snps,priority = <0x8>;
374 snps,map-to-dma-channel = <3>;
375 };
376
377 queue4 {
378 snps,dcb-algorithm;
379 snps,priority = <0xf0>;
380 snps,map-to-dma-channel = <4>;
381 };
382 };
383 };
384
385 &fec {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_fec>;
388 phy-mode = "rgmii-id";
389 phy-handle = <ðphy1>;
390 fsl,magic-packet;
391 status = "okay";
392
393 mdio {
394 #address-cells = <1>;
395 #size-cells = <0>;
396
397 ethphy1: ethernet-phy@1 {
398 compatible = "ethernet-phy-ieee802.3-c22";
399 reg = <1>;
400 eee-broken-1000t;
401 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
402 reset-assert-us = <10000>;
403 reset-deassert-us = <80000>;
404 realtek,clkout-disable;
405 };
406 };
407 };
408
409 &flexcan1 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_flexcan1>;
412 xceiver-supply = <®_can1_stby>;
413 status = "okay";
414 };
415
416 &flexcan2 {
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_flexcan2>;
419 xceiver-supply = <®_can2_stby>;
420 status = "disabled";/* can2 pin conflict with pdm */
421 };
422
423 &hdmi_pvi {
424 status = "okay";
425 };
426
427 &hdmi_tx {
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_hdmi>;
430 status = "okay";
431
432 ports {
433 port@1 {
434 hdmi_tx_out: endpoint {
435 remote-endpoint = <&hdmi_in>;
436 };
437 };
438 };
439 };
440
441 &hdmi_tx_phy {
442 status = "okay";
443 };
444
445 &i2c1 {
446 clock-frequency = <400000>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_i2c1>;
449 status = "okay";
450
451 pmic@25 {
452 compatible = "nxp,pca9450c";
453 reg = <0x25>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_pmic>;
456 interrupt-parent = <&gpio1>;
457 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
458
459 regulators {
460 BUCK1 {
461 regulator-name = "BUCK1";
462 regulator-min-microvolt = <720000>;
463 regulator-max-microvolt = <1000000>;
464 regulator-boot-on;
465 regulator-always-on;
466 regulator-ramp-delay = <3125>;
467 };
468
469 reg_arm: BUCK2 {
470 regulator-name = "BUCK2";
471 regulator-min-microvolt = <720000>;
472 regulator-max-microvolt = <1025000>;
473 regulator-boot-on;
474 regulator-always-on;
475 regulator-ramp-delay = <3125>;
476 nxp,dvs-run-voltage = <950000>;
477 nxp,dvs-standby-voltage = <850000>;
478 };
479
480 BUCK4 {
481 regulator-name = "BUCK4";
482 regulator-min-microvolt = <3000000>;
483 regulator-max-microvolt = <3600000>;
484 regulator-boot-on;
485 regulator-always-on;
486 };
487
488 reg_buck5: BUCK5 {
489 regulator-name = "BUCK5";
490 regulator-min-microvolt = <1650000>;
491 regulator-max-microvolt = <1950000>;
492 regulator-boot-on;
493 regulator-always-on;
494 };
495
496 BUCK6 {
497 regulator-name = "BUCK6";
498 regulator-min-microvolt = <1045000>;
499 regulator-max-microvolt = <1155000>;
500 regulator-boot-on;
501 regulator-always-on;
502 };
503
504 LDO1 {
505 regulator-name = "LDO1";
506 regulator-min-microvolt = <1650000>;
507 regulator-max-microvolt = <1950000>;
508 regulator-boot-on;
509 regulator-always-on;
510 };
511
512 LDO3 {
513 regulator-name = "LDO3";
514 regulator-min-microvolt = <1710000>;
515 regulator-max-microvolt = <1890000>;
516 regulator-boot-on;
517 regulator-always-on;
518 };
519
520 LDO5 {
521 regulator-name = "LDO5";
522 regulator-min-microvolt = <1800000>;
523 regulator-max-microvolt = <3300000>;
524 regulator-boot-on;
525 regulator-always-on;
526 };
527 };
528 };
529 };
530
531 &i2c2 {
532 clock-frequency = <400000>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_i2c2>;
535 status = "okay";
536
537 hdmi@3d {
538 compatible = "adi,adv7535";
539 reg = <0x3d>;
540 interrupt-parent = <&gpio1>;
541 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
542 adi,dsi-lanes = <4>;
543 avdd-supply = <®_buck5>;
544 dvdd-supply = <®_buck5>;
545 pvdd-supply = <®_buck5>;
546 a2vdd-supply = <®_buck5>;
547 v3p3-supply = <®_vext_3v3>;
548 v1p2-supply = <®_buck5>;
549
550 ports {
551 #address-cells = <1>;
552 #size-cells = <0>;
553
554 port@0 {
555 reg = <0>;
556
557 adv7535_in: endpoint {
558 remote-endpoint = <&dsi_out>;
559 };
560 };
561
562 port@1 {
563 reg = <1>;
564
565 adv7535_out: endpoint {
566 remote-endpoint = <&hdmi_connector_in>;
567 };
568 };
569
570 };
571 };
572 };
573
574 &i2c3 {
575 clock-frequency = <400000>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_i2c3>;
578 status = "okay";
579
580 wm8960: codec@1a {
581 compatible = "wlf,wm8960";
582 reg = <0x1a>;
583 #sound-dai-cells = <0>;
584 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
585 clock-names = "mclk";
586 wlf,shared-lrclk;
587 wlf,hp-cfg = <3 2 3>;
588 wlf,gpio-cfg = <1 3>;
589 SPKVDD1-supply = <®_audio_pwr>;
590 };
591
592 pca6416: gpio@20 {
593 compatible = "ti,tca6416";
594 reg = <0x20>;
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_pca6416_int>;
601 interrupt-parent = <&gpio1>;
602 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
603 gpio-line-names = "EXT_PWREN1",
604 "EXT_PWREN2",
605 "CAN1/I2C5_SEL",
606 "PDM/CAN2_SEL",
607 "FAN_EN",
608 "PWR_MEAS_IO1",
609 "PWR_MEAS_IO2",
610 "EXP_P0_7",
611 "EXP_P1_0",
612 "EXP_P1_1",
613 "EXP_P1_2",
614 "EXP_P1_3",
615 "EXP_P1_4",
616 "EXP_P1_5",
617 "EXP_P1_6",
618 "EXP_P1_7";
619 };
620 };
621
622 /* I2C on expansion connector J22. */
623 &i2c5 {
624 clock-frequency = <100000>; /* Lower clock speed for external bus. */
625 pinctrl-names = "default";
626 pinctrl-0 = <&pinctrl_i2c5>;
627 status = "disabled"; /* can1 pins conflict with i2c5 */
628
629 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
630 * LOW: CAN1 (default, pull-down)
631 * HIGH: I2C5
632 * You need to set it to high to enable I2C5 (for example, add gpio-hog
633 * in pca6416 node).
634 */
635 };
636
637 &lcdif1 {
638 status = "okay";
639 };
640
641 &lcdif3 {
642 status = "okay";
643 };
644
645 &micfil {
646 #sound-dai-cells = <0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_pdm>;
649 assigned-clocks = <&clk IMX8MP_CLK_PDM>;
650 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
651 assigned-clock-rates = <196608000>;
652 status = "okay";
653 };
654
655 &mipi_dsi {
656 samsung,esc-clock-frequency = <10000000>;
657 status = "okay";
658
659 ports {
660 port@1 {
661 reg = <1>;
662
663 dsi_out: endpoint {
664 remote-endpoint = <&adv7535_in>;
665 data-lanes = <1 2 3 4>;
666 };
667 };
668 };
669 };
670
671 &pcie_phy {
672 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
673 clocks = <&pcie0_refclk>;
674 clock-names = "ref";
675 status = "okay";
676 };
677
678 &pcie {
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_pcie0>;
681 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
682 vpcie-supply = <®_pcie0>;
683 status = "okay";
684 };
685
686 &pwm1 {
687 pinctrl-names = "default";
688 pinctrl-0 = <&pinctrl_pwm1>;
689 status = "okay";
690 };
691
692 &pwm2 {
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_pwm2>;
695 status = "okay";
696 };
697
698 &pwm4 {
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_pwm4>;
701 status = "okay";
702 };
703
704 &sai2 {
705 #sound-dai-cells = <0>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_sai2>;
708 assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
709 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
710 assigned-clock-rates = <12288000>;
711 fsl,sai-mclk-direction-output;
712 status = "okay";
713 };
714
715 &sai3 {
716 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_sai3>;
718 assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
719 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
720 assigned-clock-rates = <12288000>;
721 fsl,sai-mclk-direction-output;
722 status = "okay";
723 };
724
725 &snvs_pwrkey {
726 status = "okay";
727 };
728
729 &uart1 { /* BT */
730 pinctrl-names = "default";
731 pinctrl-0 = <&pinctrl_uart1>;
732 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
733 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
734 uart-has-rtscts;
735 status = "okay";
736 };
737
738 &uart2 {
739 /* console */
740 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_uart2>;
742 status = "okay";
743 };
744
745 &usb3_phy1 {
746 status = "okay";
747 };
748
749 &usb3_1 {
750 status = "okay";
751 };
752
753 &usb_dwc3_1 {
754 pinctrl-names = "default";
755 pinctrl-0 = <&pinctrl_usb1_vbus>;
756 dr_mode = "host";
757 status = "okay";
758 };
759
760 &uart3 {
761 pinctrl-names = "default";
762 pinctrl-0 = <&pinctrl_uart3>;
763 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
764 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
765 uart-has-rtscts;
766 status = "okay";
767 };
768
769 &usdhc2 {
770 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
771 assigned-clock-rates = <400000000>;
772 pinctrl-names = "default", "state_100mhz", "state_200mhz";
773 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
774 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
775 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
776 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
777 vmmc-supply = <®_usdhc2_vmmc>;
778 bus-width = <4>;
779 status = "okay";
780 };
781
782 &usdhc3 {
783 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
784 assigned-clock-rates = <400000000>;
785 pinctrl-names = "default", "state_100mhz", "state_200mhz";
786 pinctrl-0 = <&pinctrl_usdhc3>;
787 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
788 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
789 bus-width = <8>;
790 non-removable;
791 status = "okay";
792 };
793
794 &wdog1 {
795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_wdog>;
797 fsl,ext-reset-output;
798 status = "okay";
799 };
800
801 &xcvr {
802 #sound-dai-cells = <0>;
803 status = "okay";
804 };
805
806 &iomuxc {
807 pinctrl-names = "default";
808 pinctrl-0 = <&pinctrl_hog>;
809
810 pinctrl_audio_pwr_reg: audiopwrreggrp {
811 fsl,pins = <
812 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
813 >;
814 };
815
816 pinctrl_eqos: eqosgrp {
817 fsl,pins = <
818 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
819 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
820 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
821 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
822 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
823 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
824 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
825 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
826 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
827 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
828 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
829 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
830 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
831 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
832 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
833 >;
834 };
835
836 pinctrl_fec: fecgrp {
837 fsl,pins = <
838 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
839 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
840 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
841 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
842 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
843 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
844 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
845 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
846 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
847 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
848 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
849 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
850 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
851 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
852 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
853 >;
854 };
855
856 pinctrl_flexcan1: flexcan1grp {
857 fsl,pins = <
858 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
859 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
860 >;
861 };
862
863 pinctrl_flexcan2: flexcan2grp {
864 fsl,pins = <
865 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
866 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
867 >;
868 };
869
870 pinctrl_flexcan1_reg: flexcan1reggrp {
871 fsl,pins = <
872 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
873 >;
874 };
875
876 pinctrl_flexcan2_reg: flexcan2reggrp {
877 fsl,pins = <
878 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
879 >;
880 };
881
882 pinctrl_flexspi0: flexspi0grp {
883 fsl,pins = <
884 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
885 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
886 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
887 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
888 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
889 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
890 >;
891 };
892
893 pinctrl_gpio_led: gpioledgrp {
894 fsl,pins = <
895 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
896 >;
897 };
898
899 pinctrl_hdmi: hdmigrp {
900 fsl,pins = <
901 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
902 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
903 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
904 >;
905 };
906
907 pinctrl_hog: hoggrp {
908 fsl,pins = <
909 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
910 >;
911 };
912
913 pinctrl_i2c1: i2c1grp {
914 fsl,pins = <
915 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
916 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
917 >;
918 };
919
920 pinctrl_i2c2: i2c2grp {
921 fsl,pins = <
922 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
923 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
924 >;
925 };
926
927 pinctrl_i2c3: i2c3grp {
928 fsl,pins = <
929 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
930 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
931 >;
932 };
933
934 pinctrl_i2c5: i2c5grp {
935 fsl,pins = <
936 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
937 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
938 >;
939 };
940
941 pinctrl_pcie0: pcie0grp {
942 fsl,pins = <
943 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
944 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
945 >;
946 };
947
948 pinctrl_pcie0_reg: pcie0reggrp {
949 fsl,pins = <
950 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
951 >;
952 };
953
954 pinctrl_pdm: pdmgrp {
955 fsl,pins = <
956 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
957 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
958 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6
959 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6
960 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
961 >;
962 };
963
964 pinctrl_pmic: pmicgrp {
965 fsl,pins = <
966 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
967 >;
968 };
969
970 pinctrl_pca6416_int: pca6416_int_grp {
971 fsl,pins = <
972 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
973 >;
974 };
975
976 pinctrl_pwm1: pwm1grp {
977 fsl,pins = <
978 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
979 >;
980 };
981
982 pinctrl_pwm2: pwm2grp {
983 fsl,pins = <
984 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
985 >;
986 };
987
988 pinctrl_pwm4: pwm4grp {
989 fsl,pins = <
990 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
991 >;
992 };
993
994 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
995 fsl,pins = <
996 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
997 >;
998 };
999
1000 pinctrl_uart1: uart1grp {
1001 fsl,pins = <
1002 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
1003 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
1004 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
1005 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
1006 >;
1007 };
1008
1009 pinctrl_sai2: sai2grp {
1010 fsl,pins = <
1011 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
1012 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
1013 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
1014 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
1015 >;
1016 };
1017
1018 pinctrl_sai3: sai3grp {
1019 fsl,pins = <
1020 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
1021 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
1022 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
1023 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
1024 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
1025 >;
1026 };
1027
1028 pinctrl_uart2: uart2grp {
1029 fsl,pins = <
1030 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
1031 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
1032 >;
1033 };
1034
1035 pinctrl_usb1_vbus: usb1grp {
1036 fsl,pins = <
1037 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
1038 >;
1039 };
1040
1041 pinctrl_uart3: uart3grp {
1042 fsl,pins = <
1043 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
1044 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
1045 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
1046 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
1047 >;
1048 };
1049
1050 pinctrl_usdhc2: usdhc2grp {
1051 fsl,pins = <
1052 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
1053 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
1054 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
1055 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
1056 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
1057 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
1058 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1059 >;
1060 };
1061
1062 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1063 fsl,pins = <
1064 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
1065 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
1066 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
1067 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
1068 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
1069 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
1070 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1071 >;
1072 };
1073
1074 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1075 fsl,pins = <
1076 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
1077 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
1078 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
1079 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
1080 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
1081 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
1082 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1083 >;
1084 };
1085
1086 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
1087 fsl,pins = <
1088 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
1089 >;
1090 };
1091
1092 pinctrl_usdhc3: usdhc3grp {
1093 fsl,pins = <
1094 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1095 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1096 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1097 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1098 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1099 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1100 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1101 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1102 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1103 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1104 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1105 >;
1106 };
1107
1108 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1109 fsl,pins = <
1110 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1111 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1112 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1113 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1114 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1115 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1116 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1117 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1118 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1119 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1120 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1121 >;
1122 };
1123
1124 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1125 fsl,pins = <
1126 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1127 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1128 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1129 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1130 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1131 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1132 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1133 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1134 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1135 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1136 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1137 >;
1138 };
1139
1140 pinctrl_wdog: wdoggrp {
1141 fsl,pins = <
1142 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1143 >;
1144 };
1145 };
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