1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7 #include <dt-bindings/net/ti-dp83867.h>
8 #include "imx8mp.dtsi"
9
10 / {
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
13
14 aliases {
15 rtc0 = &rv3028;
16 rtc1 = &snvs_rtc;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0x0 0x40000000 0 0x80000000>;
22 };
23
24 reg_vdd_io: regulator-vdd-io {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
30 regulator-name = "VDD_IO";
31 };
32 };
33
34 &A53_0 {
35 cpu-supply = <&buck2>;
36 };
37
38 &A53_1 {
39 cpu-supply = <&buck2>;
40 };
41
42 &A53_2 {
43 cpu-supply = <&buck2>;
44 };
45
46 &A53_3 {
47 cpu-supply = <&buck2>;
48 };
49
50 /* ethernet 1 */
51 &fec {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec>;
54 phy-handle = <ðphy1>;
55 phy-mode = "rgmii-id";
56 fsl,magic-packet;
57 status = "okay";
58
59 mdio {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 ethphy1: ethernet-phy@0 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 reg = <0>;
66 enet-phy-lane-no-swap;
67 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
68 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
69 ti,min-output-impedance;
70 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
71 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
72 };
73 };
74 };
75
76 &flexspi {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_flexspi0>;
79 status = "okay";
80
81 som_flash: flash@0 {
82 compatible = "jedec,spi-nor";
83 reg = <0>;
84 spi-max-frequency = <80000000>;
85 spi-rx-bus-width = <4>;
86 spi-tx-bus-width = <1>;
87 };
88 };
89
90 &i2c1 {
91 clock-frequency = <400000>;
92 pinctrl-names = "default", "gpio";
93 pinctrl-0 = <&pinctrl_i2c1>;
94 pinctrl-1 = <&pinctrl_i2c1_gpio>;
95 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
96 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
97 status = "okay";
98
99 pmic: pmic@25 {
100 compatible = "nxp,pca9450c";
101 reg = <0x25>;
102 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
103 interrupt-parent = <&gpio4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_pmic>;
106
107 regulators {
108 buck1: BUCK1 {
109 regulator-always-on;
110 regulator-boot-on;
111 regulator-max-microvolt = <1000000>;
112 regulator-min-microvolt = <805000>;
113 regulator-name = "VDD_SOC (BUCK1)";
114 regulator-ramp-delay = <3125>;
115 };
116
117 buck2: BUCK2 {
118 nxp,dvs-run-voltage = <950000>;
119 nxp,dvs-standby-voltage = <850000>;
120 regulator-always-on;
121 regulator-boot-on;
122 regulator-max-microvolt = <1050000>;
123 regulator-min-microvolt = <805000>;
124 regulator-name = "VDD_ARM (BUCK2)";
125 regulator-ramp-delay = <3125>;
126 };
127
128 buck4: BUCK4 {
129 regulator-always-on;
130 regulator-boot-on;
131 regulator-max-microvolt = <3300000>;
132 regulator-min-microvolt = <3300000>;
133 regulator-name = "VDD_3V3 (BUCK4)";
134 };
135
136 buck5: BUCK5 {
137 regulator-always-on;
138 regulator-boot-on;
139 regulator-max-microvolt = <1800000>;
140 regulator-min-microvolt = <1800000>;
141 regulator-name = "VDD_1V8 (BUCK5)";
142 };
143
144 buck6: BUCK6 {
145 regulator-always-on;
146 regulator-boot-on;
147 regulator-max-microvolt = <1155000>;
148 regulator-min-microvolt = <1045000>;
149 regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
150 };
151
152 ldo1: LDO1 {
153 regulator-always-on;
154 regulator-boot-on;
155 regulator-max-microvolt = <1950000>;
156 regulator-min-microvolt = <1710000>;
157 regulator-name = "NVCC_SNVS_1V8 (LDO1)";
158 };
159
160 ldo3: LDO3 {
161 regulator-always-on;
162 regulator-boot-on;
163 regulator-max-microvolt = <1800000>;
164 regulator-min-microvolt = <1800000>;
165 regulator-name = "VDDA_1V8 (LDO3)";
166 };
167
168 ldo5: LDO5 {
169 regulator-always-on;
170 regulator-boot-on;
171 regulator-max-microvolt = <3300000>;
172 regulator-min-microvolt = <1800000>;
173 regulator-name = "NVCC_SD2 (LDO5)";
174 };
175 };
176 };
177
178 eeprom@51 {
179 compatible = "atmel,24c32";
180 reg = <0x51>;
181 pagesize = <32>;
182 vcc-supply = <®_vdd_io>;
183 };
184
185 rv3028: rtc@52 {
186 compatible = "microcrystal,rv3028";
187 reg = <0x52>;
188 };
189 };
190
191 /* eMMC */
192 &usdhc3 {
193 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
194 assigned-clock-rates = <400000000>;
195 pinctrl-names = "default", "state_100mhz", "state_200mhz";
196 pinctrl-0 = <&pinctrl_usdhc3>;
197 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
198 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
199 bus-width = <8>;
200 non-removable;
201 status = "okay";
202 };
203
204 &wdog1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_wdog>;
207 fsl,ext-reset-output;
208 status = "okay";
209 };
210
211 &gpio1 {
212 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
213 "", "", "", "", "", "",
214 "", "", "", "", "", "X_nETHPHY_INT";
215 };
216
217 &gpio4 {
218 gpio-line-names = "", "", "", "",
219 "", "", "", "", "", "",
220 "", "", "", "", "", "",
221 "", "", "X_PMIC_IRQ_B";
222 };
223
224 &iomuxc {
225 pinctrl_fec: fecgrp {
226 fsl,pins = <
227 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
228 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
229 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
230 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
231 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
232 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
233 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
234 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
235 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
236 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
237 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
238 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
239 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
240 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
241 >;
242 };
243
244 pinctrl_flexspi0: flexspi0grp {
245 fsl,pins = <
246 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
247 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
248 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
249 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
250 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
251 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
252 >;
253 };
254
255 pinctrl_i2c1: i2c1grp {
256 fsl,pins = <
257 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
258 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
259 >;
260 };
261
262 pinctrl_i2c1_gpio: i2c1gpiogrp {
263 fsl,pins = <
264 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2
265 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2
266 >;
267 };
268
269 pinctrl_pmic: pmicirqgrp {
270 fsl,pins = <
271 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140
272 >;
273 };
274
275 pinctrl_usdhc3: usdhc3grp {
276 fsl,pins = <
277 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
278 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
279 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
280 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
281 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
282 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
283 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
284 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
285 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
286 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
287 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
288 >;
289 };
290
291 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
292 fsl,pins = <
293 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
294 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
295 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
296 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
297 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
298 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
299 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
300 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
301 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
302 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
303 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
304 >;
305 };
306
307 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
308 fsl,pins = <
309 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
310 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
311 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
312 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
313 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
314 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
315 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
316 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
317 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
318 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
319 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
320 >;
321 };
322
323 pinctrl_wdog: wdoggrp {
324 fsl,pins = <
325 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
326 >;
327 };
328 };
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