1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /*
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Martin Schmiedel
6 * Author: Alexander Stein
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
16
17 / {
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
19 compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
20 chassis-type = "embedded";
21
22 chosen {
23 stdout-path = &uart4;
24 };
25
26 aliases {
27 mmc0 = &usdhc3;
28 mmc1 = &usdhc2;
29 mmc2 = &usdhc1;
30 rtc0 = &pcf85063;
31 rtc1 = &snvs_rtc;
32 };
33
34 /* X8 */
35 backlight_lvds: backlight {
36 compatible = "pwm-backlight";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_backlight>;
39 pwms = <&pwm2 0 5000000 0>;
40 brightness-levels = <0 4 8 16 32 64 128 255>;
41 default-brightness-level = <7>;
42 power-supply = <®_vcc_12v0>;
43 enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
44 status = "disabled";
45 };
46
47 /* X7 + X8 */
48 display: display {
49 /*
50 * Display is not fixed, so compatible has to be added from
51 * DT overlay
52 */
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_lvdsdisplay>;
55 power-supply = <®_vcc_3v3>;
56 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
57 backlight = <&backlight_lvds>;
58 status = "disabled";
59 };
60
61 gpio-leds {
62 compatible = "gpio-leds";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_gpioled>;
65
66 led-1 {
67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTION_STATUS;
69 function-enumerator = <0>;
70 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
71 };
72
73 led-2 {
74 color = <LED_COLOR_ID_YELLOW>;
75 function = LED_FUNCTION_STATUS;
76 function-enumerator = <1>;
77 gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
78 };
79 };
80
81 hdmi-connector {
82 compatible = "hdmi-connector";
83 label = "X9";
84 type = "a";
85
86 port {
87 hdmi_connector_in: endpoint {
88 remote-endpoint = <&hdmi_tx_out>;
89 };
90 };
91 };
92
93 reg_usdhc2_vmmc: regulator-usdhc2 {
94 compatible = "regulator-fixed";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
97 regulator-name = "VSD_3V3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
101 enable-active-high;
102 startup-delay-us = <100>;
103 off-on-delay-us = <12000>;
104 };
105
106 reg_vcc_3v3: regulator-3v3 {
107 compatible = "regulator-fixed";
108 regulator-name = "V_3V3";
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 };
112
113 reg_vcc_5v0: regulator-5v0 {
114 compatible = "regulator-fixed";
115 regulator-name = "V_5V0";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
118 };
119
120 reg_vcc_12v0: regulator-12v0 {
121 compatible = "regulator-fixed";
122 regulator-name = "V_12V";
123 regulator-min-microvolt = <12000000>;
124 regulator-max-microvolt = <12000000>;
125 };
126
127 reserved-memory {
128 #address-cells = <2>;
129 #size-cells = <2>;
130 ranges;
131
132 /* global autoconfigured region for contiguous allocations */
133 linux,cma {
134 compatible = "shared-dma-pool";
135 reusable;
136 size = <0 0x38000000>;
137 alloc-ranges = <0 0x40000000 0 0xB0000000>;
138 linux,cma-default;
139 };
140 };
141
142 rfkill {
143 compatible = "rfkill-gpio";
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_rfkill>;
146 label = "rfkill-pcie-wlan";
147 radio-type = "wlan";
148 shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
149 };
150
151 sound {
152 compatible = "fsl,imx-audio-tlv320aic32x4";
153 model = "tq-mba8mp-ras314";
154 audio-cpu = <&sai5>;
155 audio-codec = <&tlv320aic3x04>;
156 audio-routing =
157 "IN3_L", "Mic Jack",
158 "Mic Jack", "Mic Bias",
159 "Headphone Jack", "HPL",
160 "Headphone Jack", "HPR";
161 };
162 };
163
164 &ecspi3 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_ecspi3>;
167 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>;
168 status = "okay";
169 };
170
171 &eqos {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_eqos>;
174 phy-mode = "rgmii-id";
175 phy-handle = <ðphy3>;
176 status = "okay";
177
178 mdio {
179 compatible = "snps,dwmac-mdio";
180 #address-cells = <1>;
181 #size-cells = <0>;
182
183 ethphy3: ethernet-phy@3 {
184 compatible = "ethernet-phy-ieee802.3-c22";
185 reg = <3>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_eqos_phy>;
188 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
189 reset-assert-us = <500000>;
190 reset-deassert-us = <50000>;
191 enet-phy-lane-no-swap;
192 interrupt-parent = <&gpio4>;
193 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
194 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
195 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
196 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
197 ti,dp83867-rxctrl-strap-quirk;
198 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
199 };
200 };
201 };
202
203 &fec {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_fec>;
206 phy-mode = "rgmii-id";
207 phy-handle = <ðphy0>;
208 fsl,magic-packet;
209 status = "okay";
210
211 mdio {
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 ethphy0: ethernet-phy@0 {
216 compatible = "ethernet-phy-ieee802.3-c22";
217 reg = <0>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec_phy>;
220 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
221 reset-assert-us = <500000>;
222 reset-deassert-us = <50000>;
223 enet-phy-lane-no-swap;
224 interrupt-parent = <&gpio4>;
225 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
226 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
227 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
228 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
229 ti,dp83867-rxctrl-strap-quirk;
230 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
231 };
232 };
233 };
234
235 &gpio1 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_gpio1>;
238
239 gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "",
240 "", "", "GPIO8", "",
241 "", "", "", "",
242 "", "", "GPIO12", "GPIO13",
243 "", "", "", "",
244 "", "", "", "",
245 "", "", "", "",
246 "", "", "", "";
247
248 wifi-pmic-en-hog {
249 gpio-hog;
250 gpios = <0 0>;
251 output-high;
252 line-name = "WIFI_PMIC_EN";
253 };
254 };
255
256 &gpio2 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_gpio2>;
259
260 gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25",
261 "GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2",
262 "", "", "GPIO1", "GPIO0",
263 "", "", "", "",
264 "", "", "", "",
265 "", "", "", "",
266 "", "", "", "",
267 "", "", "", "";
268 };
269
270 &gpio3 {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_gpio3>;
273
274 gpio-line-names = "", "", "", "",
275 "", "", "", "",
276 "", "", "", "",
277 "", "", "", "",
278 "", "", "", "",
279 "TEMP_EVENT#", "", "", "",
280 "", "", "", "",
281 "", "", "", "";
282 };
283
284 &gpio4 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_gpio4>;
287
288 gpio-line-names = "", "", "", "",
289 "", "", "", "",
290 "", "", "", "",
291 "", "", "", "",
292 "", "", "", "",
293 "HDMI_OC#", "GPIO14", "GPIO15", "GPIO16",
294 "GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20",
295 "PCIE_PERST#", "", "", "";
296
297 pewake-hog {
298 gpio-hog;
299 gpios = <25 0>;
300 input;
301 line-name = "PCIE_WAKE#";
302 };
303 };
304
305 &gpio5 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>,
308 <&pinctrl_gpt2_gpio>, <&pinctrl_gpt3_gpio>;
309
310 gpio-line-names = "", "GPIO18", "", "GPIO3",
311 "GPIO2", "GPIO21", "", "",
312 "", "", "", "",
313 "", "", "", "",
314 "", "", "GPIO5", "GPIO6",
315 "", "", "GPIO11", "GPIO10",
316 "GPIO9", "GPIO7", "", "GPIO4",
317 "", "", "", "";
318 };
319
320 &gpt1 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_gpt1>;
323 status = "disabled";
324 };
325
326 &gpt2 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_gpt2>;
329 status = "disabled";
330 };
331
332 &gpt3 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_gpt3>;
335 status = "disabled";
336 };
337
338 &hdmi_pvi {
339 status = "okay";
340 };
341
342 &hdmi_tx {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_hdmi>;
345 status = "okay";
346
347 ports {
348 port@1 {
349 hdmi_tx_out: endpoint {
350 remote-endpoint = <&hdmi_connector_in>;
351 };
352 };
353 };
354 };
355
356 &hdmi_tx_phy {
357 status = "okay";
358 };
359
360 /* X5 + X6 Camera & Display interface */
361 &i2c2 {
362 clock-frequency = <384000>;
363 pinctrl-names = "default", "gpio";
364 pinctrl-0 = <&pinctrl_i2c2>;
365 pinctrl-1 = <&pinctrl_i2c2_gpio>;
366 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
367 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
368 status = "okay";
369 };
370
371 /* X1 ID_I2C */
372 &i2c3 {
373 clock-frequency = <384000>;
374 pinctrl-names = "default", "gpio";
375 pinctrl-0 = <&pinctrl_i2c3>;
376 pinctrl-1 = <&pinctrl_i2c3_gpio>;
377 scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
378 sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
379 status = "okay";
380 };
381
382 &i2c4 {
383 clock-frequency = <384000>;
384 pinctrl-names = "default", "gpio";
385 pinctrl-0 = <&pinctrl_i2c4>;
386 pinctrl-1 = <&pinctrl_i2c4_gpio>;
387 scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
388 sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
389 status = "okay";
390
391 tlv320aic3x04: audio-codec@18 {
392 compatible = "ti,tlv320aic32x4";
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_tlv320aic3x04>;
395 reg = <0x18>;
396 clock-names = "mclk";
397 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
398 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
399 iov-supply = <®_vcc_3v3>;
400 ldoin-supply = <®_vcc_3v3>;
401 };
402 };
403
404 /* X1 I2C */
405 &i2c5 {
406 clock-frequency = <384000>;
407 pinctrl-names = "default", "gpio";
408 pinctrl-0 = <&pinctrl_i2c5>;
409 pinctrl-1 = <&pinctrl_i2c5_gpio>;
410 scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
411 sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
412 status = "okay";
413 };
414
415 /* X1 I2C on GPIO24/GPIO25 */
416 &i2c6 {
417 clock-frequency = <384000>;
418 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c6>;
420 pinctrl-1 = <&pinctrl_i2c6_gpio>;
421 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
422 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
423 status = "disabled";
424 };
425
426 &lcdif3 {
427 status = "okay";
428 };
429
430 &pcf85063 {
431 /* RTC_EVENT# is connected on MBa8MP-RAS314 */
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_pcf85063>;
434 interrupt-parent = <&gpio3>;
435 interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
436 };
437
438 &pcie_phy {
439 clocks = <&hsio_blk_ctrl>;
440 clock-names = "ref";
441 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
442 status = "okay";
443 };
444
445 &pcie {
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_pcie>;
448 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
449 status = "okay";
450 };
451
452 &pwm2 {
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_pwm2>;
455 status = "disabled";
456 };
457
458 &pwm3 {
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_pwm3>;
461 status = "okay";
462 };
463
464 &pwm4 {
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_pwm4>;
467 status = "okay";
468 };
469
470 &sai5 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_sai5>;
473 assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
474 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
475 assigned-clock-rates = <12288000>;
476 fsl,sai-mclk-direction-output;
477 status = "okay";
478 };
479
480 &snvs_pwrkey {
481 status = "okay";
482 };
483
484 /* X1 UART1 */
485 &uart1 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_uart1>;
488 uart-has-rtscts;
489 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
490 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
491 status = "okay";
492 };
493
494 &uart2 {
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart2>;
497 uart-has-rtscts;
498 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
499 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
500 status = "okay";
501
502 bluetooth {
503 compatible = "nxp,88w8987-bt";
504 };
505 };
506
507 &uart3 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart3>;
510 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
511 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
512 status = "okay";
513 };
514
515 &uart4 {
516 /* console */
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_uart4>;
519 status = "okay";
520 };
521
522 &usb3_0 {
523 fsl,disable-port-power-control;
524 status = "okay";
525 };
526
527 &usb3_1 {
528 fsl,disable-port-power-control;
529 fsl,permanently-attached;
530 status = "okay";
531 };
532
533 &usb3_phy0 {
534 vbus-supply = <®_vcc_5v0>;
535 status = "okay";
536 };
537
538 &usb3_phy1 {
539 vbus-supply = <®_vcc_5v0>;
540 status = "okay";
541 };
542
543 &usb_dwc3_0 {
544 dr_mode = "peripheral";
545 status = "okay";
546 };
547
548 &usb_dwc3_1 {
549 dr_mode = "host";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_usbhub>;
554 status = "okay";
555
556 hub_2_0: hub@1 {
557 compatible = "usb451,8142";
558 reg = <1>;
559 peer-hub = <&hub_3_0>;
560 reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
561 vdd-supply = <®_vcc_3v3>;
562 };
563
564 hub_3_0: hub@2 {
565 compatible = "usb451,8140";
566 reg = <2>;
567 peer-hub = <&hub_2_0>;
568 reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
569 vdd-supply = <®_vcc_3v3>;
570 };
571 };
572
573 /* X1 SD card on GPIO22-GPIO27 */
574 &usdhc1 {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_usdhc1>;
577 disable-wp;
578 bus-width = <4>;
579 status = "disabled";
580 };
581
582 &usdhc2 {
583 pinctrl-names = "default", "state_100mhz", "state_200mhz";
584 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
585 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
586 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
587 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
588 vmmc-supply = <®_usdhc2_vmmc>;
589 no-mmc;
590 no-sdio;
591 disable-wp;
592 bus-width = <4>;
593 status = "okay";
594 };
595
596 &iomuxc {
597 pinctrl_backlight: backlightgrp {
598 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x14>;
599 };
600
601 pinctrl_ecspi3: ecspi3grp {
602 fsl,pins = <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x140>,
603 <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x140>,
604 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
605 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x140>,
606 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140>;
607 };
608
609 pinctrl_ecspi3_gpio: ecspi3gpiogrp {
610 fsl,pins = <MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x80>,
611 <MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x80>,
612 <MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x80>,
613 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x80>,
614 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x80>;
615 };
616
617 pinctrl_eqos: eqosgrp {
618 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
619 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
620 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
621 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
622 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
623 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
624 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
625 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
626 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
627 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
628 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
629 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
630 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
631 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
632 };
633
634 pinctrl_eqos_phy: eqosphygrp {
635 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
636 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
637 };
638
639 pinctrl_fec: fecgrp {
640 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
641 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
642 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
643 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
644 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
645 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
646 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
647 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
648 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
649 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
650 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
651 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
652 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
653 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
654 };
655
656 pinctrl_fec_phy: fecphygrp {
657 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
658 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
659 };
660
661 pinctrl_gpioled: gpioledgrp {
662 fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>,
663 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>;
664 };
665
666 pinctrl_gpio1: gpio1grp {
667 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x14>,
668 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x14>;
669 };
670
671 pinctrl_gpio2: gpio2grp {
672 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x94>,
673 <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x94>,
674 <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x94>,
675 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x94>,
676 <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x94>,
677 <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x94>,
678 <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x94>,
679 <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x94>;
680 };
681
682 pinctrl_gpio3: gpio3grp {
683 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>;
684 };
685
686 pinctrl_gpio4: gpio4grp {
687 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x80>,
688 /* PCIE_WAKE# */
689 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>,
690 <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x94>,
691 <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x94>;
692 };
693
694 pinctrl_gpio5: gpio5grp {
695 fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x80>,
696 <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x80>;
697 };
698
699 pinctrl_hdmi: hdmigrp {
700 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
701 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
702 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
703 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>;
704 };
705
706 pinctrl_gpt1: gpt1grp {
707 fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>;
708 };
709
710 pinctrl_gpt1_gpio: gpt1gpiogrp {
711 fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x80>;
712 };
713
714 pinctrl_gpt2: gpt2grp {
715 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>;
716 };
717
718 pinctrl_gpt2_gpio: gpt2gpiogrp {
719 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>;
720 };
721
722 pinctrl_gpt3: gpt3grp {
723 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>;
724 };
725
726 pinctrl_gpt3_gpio: gpt3gpiogrp {
727 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x80>;
728 };
729
730 pinctrl_i2c2: i2c2grp {
731 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
732 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
733 };
734
735 pinctrl_i2c2_gpio: i2c2-gpiogrp {
736 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
737 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
738 };
739
740 pinctrl_i2c3: i2c3grp {
741 fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>,
742 <MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>;
743 };
744
745 pinctrl_i2c3_gpio: i2c3-gpiogrp {
746 fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>,
747 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>;
748 };
749
750 pinctrl_i2c4: i2c4grp {
751 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>,
752 <MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>;
753 };
754
755 pinctrl_i2c4_gpio: i2c4-gpiogrp {
756 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>,
757 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>;
758 };
759
760 pinctrl_i2c5: i2c5grp {
761 fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>,
762 <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>;
763 };
764
765 pinctrl_i2c5_gpio: i2c5-gpiogrp {
766 fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>,
767 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>;
768 };
769
770 pinctrl_i2c6: i2c6grp {
771 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
772 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
773 };
774
775 pinctrl_i2c6_gpio: i2c6-gpiogrp {
776 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
777 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
778 };
779
780 pinctrl_pcf85063: pcf85063grp {
781 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>;
782 };
783
784 pinctrl_pcie: pciegrp {
785 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
786 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x94>;
787 };
788
789 pinctrl_lvdsdisplay: lvdsdisplaygrp {
790 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10>;
791 };
792
793 pinctrl_pwm2: pwm2grp {
794 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x14>;
795 };
796
797 pinctrl_pwm3: pwm3grp {
798 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>;
799 };
800
801 pinctrl_pwm3_gpio: pwm3grpiogrp {
802 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>;
803 };
804
805 pinctrl_pwm4: pwm4grp {
806 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>;
807 };
808
809 pinctrl_pwm4_gpio: pwm4grpiogrp {
810 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
811 };
812
813 pinctrl_rfkill: rfkillgrp {
814 fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x14>;
815 };
816
817 pinctrl_sai5: sai5grp {
818 fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>,
819 <MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>,
820 <MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>,
821 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>,
822 <MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>;
823 };
824
825 pinctrl_tlv320aic3x04: tlv320aic3x04grp {
826 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>;
827 };
828
829 pinctrl_uart1: uart1grp {
830 fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
831 <MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
832 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
833 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
834 };
835
836 pinctrl_uart1_gpio: uart1gpiogrp {
837 fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x80>,
838 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x80>,
839 <MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x80>,
840 <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x80>;
841 };
842
843 pinctrl_uart2: uart2grp {
844 fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>,
845 <MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>,
846 <MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x14>,
847 <MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x14>;
848 };
849
850 pinctrl_uart3: uart3grp {
851 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
852 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
853 };
854
855 pinctrl_uart4: uart4grp {
856 fsl,pins = <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>,
857 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>;
858 };
859
860 pinctrl_usbhub: usbhubgrp {
861 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>;
862 };
863
864 pinctrl_usdhc1: usdhc1grp {
865 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>,
866 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>,
867 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>,
868 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>,
869 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>,
870 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>;
871 };
872
873 pinctrl_usdhc2: usdhc2grp {
874 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
875 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
876 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
877 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
878 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
879 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
880 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
881 };
882
883 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
884 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
885 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
886 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
887 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
888 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
889 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
890 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
891 };
892
893 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
894 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
895 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
896 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
897 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
898 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
899 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
900 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
901 };
902
903 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
904 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
905 };
906 };
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