1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /*
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
5 */
6
7 #include "imx8mp.dtsi"
8
9 / {
10 model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
11 compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
12
13 memory@40000000 {
14 device_type = "memory";
15 reg = <0x0 0x40000000 0 0x80000000>;
16 };
17
18 /* identical to buck4_reg, but should never change */
19 reg_vcc3v3: regulator-vcc3v3 {
20 compatible = "regulator-fixed";
21 regulator-name = "VCC3V3";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 regulator-always-on;
25 };
26
27 /* e-MMC IO, needed for HS modes */
28 reg_vcc1v8: regulator-vcc1v8 {
29 compatible = "regulator-fixed";
30 regulator-name = "VCC1V8";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-always-on;
34 };
35 };
36
37 &A53_0 {
38 cpu-supply = <&buck2_reg>;
39 };
40
41 &flexspi {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_flexspi0>;
44 status = "okay";
45
46 flash0: flash@0 {
47 reg = <0>;
48 compatible = "jedec,spi-nor";
49 spi-max-frequency = <80000000>;
50 spi-tx-bus-width = <1>;
51 spi-rx-bus-width = <4>;
52
53 partitions {
54 compatible = "fixed-partitions";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 };
58 };
59 };
60
61 &i2c1 {
62 clock-frequency = <384000>;
63 pinctrl-names = "default", "gpio";
64 pinctrl-0 = <&pinctrl_i2c1>;
65 pinctrl-1 = <&pinctrl_i2c1_gpio>;
66 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
67 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
68 status = "okay";
69
70 se97: temperature-sensor@1b {
71 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
72 reg = <0x1b>;
73 };
74
75 pmic: pmic@25 {
76 reg = <0x25>;
77 compatible = "nxp,pca9450c";
78
79 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
80 pinctrl-0 = <&pinctrl_pmic>;
81 pinctrl-names = "default";
82 interrupt-parent = <&gpio1>;
83 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
84
85 regulators {
86 /* V_0V85_SOC: 0.85 .. 0.95 */
87 buck1_reg: BUCK1 {
88 regulator-name = "BUCK1";
89 regulator-min-microvolt = <850000>;
90 regulator-max-microvolt = <950000>;
91 regulator-boot-on;
92 regulator-always-on;
93 regulator-ramp-delay = <3125>;
94 };
95
96 /* VDD_ARM */
97 buck2_reg: BUCK2 {
98 regulator-name = "BUCK2";
99 regulator-min-microvolt = <850000>;
100 regulator-max-microvolt = <1000000>;
101 regulator-boot-on;
102 regulator-always-on;
103 nxp,dvs-run-voltage = <950000>;
104 nxp,dvs-standby-voltage = <850000>;
105 regulator-ramp-delay = <3125>;
106 };
107
108 /* VCC3V3 -> VMMC, ... must not be changed */
109 buck4_reg: BUCK4 {
110 regulator-name = "BUCK4";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 regulator-boot-on;
114 regulator-always-on;
115 };
116
117 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
118 buck5_reg: BUCK5 {
119 regulator-name = "BUCK5";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-boot-on;
123 regulator-always-on;
124 };
125
126 /* V_1V1 -> RAM, ... must not be changed */
127 buck6_reg: BUCK6 {
128 regulator-name = "BUCK6";
129 regulator-min-microvolt = <1100000>;
130 regulator-max-microvolt = <1100000>;
131 regulator-boot-on;
132 regulator-always-on;
133 };
134
135 /* V_1V8_SNVS */
136 ldo1_reg: LDO1 {
137 regulator-name = "LDO1";
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
140 regulator-boot-on;
141 regulator-always-on;
142 };
143
144 /* V_1V8_ANA */
145 ldo3_reg: LDO3 {
146 regulator-name = "LDO3";
147 regulator-min-microvolt = <1800000>;
148 regulator-max-microvolt = <1800000>;
149 regulator-boot-on;
150 regulator-always-on;
151 };
152
153 /* unused */
154 ldo4_reg: LDO4 {
155 regulator-name = "LDO4";
156 regulator-min-microvolt = <800000>;
157 regulator-max-microvolt = <3300000>;
158 };
159
160 /* VCC SD IO - switched using SD2 VSELECT */
161 ldo5_reg: LDO5 {
162 regulator-name = "LDO5";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
165 };
166 };
167 };
168
169 pcf85063: rtc@51 {
170 compatible = "nxp,pcf85063a";
171 reg = <0x51>;
172 };
173
174 at24c02: eeprom@53 {
175 compatible = "nxp,se97b", "atmel,24c02";
176 read-only;
177 reg = <0x53>;
178 pagesize = <16>;
179 vcc-supply = <®_vcc3v3>;
180 };
181
182 m24c64: eeprom@57 {
183 compatible = "atmel,24c64";
184 reg = <0x57>;
185 pagesize = <32>;
186 vcc-supply = <®_vcc3v3>;
187 };
188 };
189
190 &usdhc3 {
191 pinctrl-names = "default", "state_100mhz", "state_200mhz";
192 pinctrl-0 = <&pinctrl_usdhc3>;
193 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
194 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
195 bus-width = <8>;
196 non-removable;
197 no-sd;
198 no-sdio;
199 vmmc-supply = <®_vcc3v3>;
200 vqmmc-supply = <®_vcc1v8>;
201 status = "okay";
202 };
203
204 &wdog1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_wdog>;
207 fsl,ext-reset-output;
208 status = "okay";
209 };
210
211 &iomuxc {
212 pinctrl_flexspi0: flexspi0grp {
213 fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>,
214 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
215 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
216 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
217 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
218 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>;
219 };
220
221 pinctrl_i2c1: i2c1grp {
222 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>,
223 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>;
224 };
225
226 pinctrl_i2c1_gpio: i2c1-gpiogrp {
227 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>,
228 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>;
229 };
230
231 pinctrl_pmic: pmicirqgrp {
232 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>;
233 };
234
235 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
236 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
237 };
238
239 pinctrl_usdhc3: usdhc3grp {
240 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
241 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
242 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
243 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
244 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
245 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
246 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
247 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
248 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
249 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
250 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
251 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
252 };
253
254 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
255 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
256 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
257 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
258 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
259 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
260 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
261 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
262 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
263 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
264 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
265 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
266 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
267 };
268
269 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
270 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
271 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
272 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
273 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
274 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
275 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
276 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
277 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
278 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
279 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
280 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
281 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
282 };
283
284 pinctrl_wdog: wdoggrp {
285 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>;
286 };
287 };
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