1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9
10 / {
11 aliases {
12 ethernet1 = ð1;
13 };
14
15 connector {
16 compatible = "gpio-usb-b-connector", "usb-b-connector";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usbcon1>;
19 type = "micro";
20 label = "otg";
21 vbus-supply = <®_usb1_vbus>;
22 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
23
24 port {
25 usb_dr_connector: endpoint {
26 remote-endpoint = <&usb3_dwc>;
27 };
28 };
29 };
30
31 led-controller {
32 compatible = "gpio-leds";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_leds>;
35
36 led-0 {
37 function = LED_FUNCTION_STATUS;
38 color = <LED_COLOR_ID_GREEN>;
39 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
40 default-state = "on";
41 linux,default-trigger = "heartbeat";
42 };
43
44 led-1 {
45 function = LED_FUNCTION_STATUS;
46 color = <LED_COLOR_ID_RED>;
47 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
48 default-state = "off";
49 };
50 };
51
52 pcie0_refclk: clock-pcie0 {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <100000000>;
56 };
57
58 pps {
59 compatible = "pps-gpio";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pps>;
62 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
63 status = "okay";
64 };
65
66 reg_usb1_vbus: regulator-usb1 {
67 compatible = "regulator-fixed";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_reg_usb1_en>;
70 regulator-name = "usb1_vbus";
71 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 };
76
77 reg_usb2_vbus: regulator-usb2 {
78 compatible = "regulator-fixed";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_reg_usb2_en>;
81 regulator-name = "usb2_vbus";
82 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <5000000>;
86 };
87
88 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
89 compatible = "regulator-fixed";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
92 regulator-name = "VDD_3V3_SD";
93 enable-active-high;
94 gpio = <&gpio2 19 0>; /* SD2_RESET */
95 off-on-delay-us = <12000>;
96 regulator-max-microvolt = <3300000>;
97 regulator-min-microvolt = <3300000>;
98 startup-delay-us = <100>;
99 };
100 };
101
102 /* off-board header */
103 &ecspi2 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_spi2>;
106 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
107 <&gpio1 10 GPIO_ACTIVE_LOW>;
108 status = "okay";
109
110 tpm@1 {
111 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
112 reg = <0x1>;
113 spi-max-frequency = <36000000>;
114 };
115 };
116
117 &gpio4 {
118 gpio-line-names =
119 "", "", "", "",
120 "", "", "", "",
121 "dio1", "", "", "dio0",
122 "", "", "pci_usb_sel", "",
123 "", "", "", "",
124 "", "", "rs485_en", "rs485_term",
125 "", "", "", "rs485_half",
126 "pci_wdis#", "", "", "";
127 };
128
129 &i2c2 {
130 clock-frequency = <400000>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c2>;
133 status = "okay";
134
135 accelerometer@19 {
136 compatible = "st,lis2de12";
137 reg = <0x19>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_accel>;
140 st,drdy-int-pin = <1>;
141 interrupt-parent = <&gpio4>;
142 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
143 };
144 };
145
146 &pcie_phy {
147 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
148 fsl,clkreq-unsupported;
149 clocks = <&pcie0_refclk>;
150 clock-names = "ref";
151 status = "okay";
152 };
153
154 &pcie {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_pcie0>;
157 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
158 status = "okay";
159
160 pcie@0,0 {
161 reg = <0x0000 0 0 0 0>;
162 device_type = "pci";
163 #address-cells = <3>;
164 #size-cells = <2>;
165 ranges;
166
167 pcie@0,0 {
168 reg = <0x0000 0 0 0 0>;
169 device_type = "pci";
170 #address-cells = <3>;
171 #size-cells = <2>;
172 ranges;
173
174 pcie@3,0 {
175 reg = <0x1800 0 0 0 0>;
176 device_type = "pci";
177 #address-cells = <3>;
178 #size-cells = <2>;
179 ranges;
180
181 eth1: ethernet@0,0 {
182 reg = <0x0000 0 0 0 0>;
183 #address-cells = <3>;
184 #size-cells = <2>;
185 ranges;
186 local-mac-address = [00 00 00 00 00 00];
187 };
188 };
189 };
190 };
191 };
192
193 /* GPS */
194 &uart1 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_uart1>;
197 status = "okay";
198 };
199
200 /* off-board header */
201 &uart3 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart3>;
204 status = "okay";
205 };
206
207 /* RS232 */
208 &uart4 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart4>;
211 status = "okay";
212 };
213
214 /* USB1 - OTG */
215 &usb3_0 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_usb1>;
218 fsl,over-current-active-low;
219 status = "okay";
220 };
221
222 &usb3_phy0 {
223 status = "okay";
224 };
225
226 &usb_dwc3_0 {
227 /* dual role is implemented but not a full featured OTG */
228 adp-disable;
229 hnp-disable;
230 srp-disable;
231 dr_mode = "otg";
232 usb-role-switch;
233 role-switch-default-mode = "peripheral";
234 status = "okay";
235
236 port {
237 usb3_dwc: endpoint {
238 remote-endpoint = <&usb_dr_connector>;
239 };
240 };
241 };
242
243 /* USB2 - USB3.0 Hub */
244 &usb3_1 {
245 fsl,permanently-attached;
246 fsl,disable-port-power-control;
247 status = "okay";
248 };
249
250 &usb3_phy1 {
251 vbus-supply = <®_usb2_vbus>;
252 status = "okay";
253 };
254
255 &usb_dwc3_1 {
256 dr_mode = "host";
257 status = "okay";
258 };
259
260 /* microSD */
261 &usdhc2 {
262 pinctrl-names = "default", "state_100mhz", "state_200mhz";
263 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
264 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
265 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
266 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
267 bus-width = <4>;
268 vmmc-supply = <®_usdhc2_vmmc>;
269 status = "okay";
270 };
271
272 &iomuxc {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_hog>;
275
276 pinctrl_hog: hoggrp {
277 fsl,pins = <
278 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
279 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
280 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
281 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
282 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
283 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
284 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
285 >;
286 };
287
288 pinctrl_accel: accelgrp {
289 fsl,pins = <
290 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
291 >;
292 };
293
294 pinctrl_gpio_leds: gpioledgrp {
295 fsl,pins = <
296 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
297 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
298 >;
299 };
300
301 pinctrl_pcie0: pcie0grp {
302 fsl,pins = <
303 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
304 >;
305 };
306
307 pinctrl_pps: ppsgrp {
308 fsl,pins = <
309 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
310 >;
311 };
312
313 pinctrl_reg_usb1_en: regusb1grp {
314 fsl,pins = <
315 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
316 >;
317 };
318
319 pinctrl_usb1: usb1grp {
320 fsl,pins = <
321 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
322 >;
323 };
324
325 pinctrl_usbcon1: usbcon1grp {
326 fsl,pins = <
327 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
328 >;
329 };
330
331 pinctrl_reg_usb2_en: regusb2grp {
332 fsl,pins = <
333 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
334 >;
335 };
336
337 pinctrl_spi2: spi2grp {
338 fsl,pins = <
339 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
340 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
341 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
342 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
343 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
344 >;
345 };
346
347 pinctrl_uart1: uart1grp {
348 fsl,pins = <
349 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
350 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
351 >;
352 };
353
354 pinctrl_uart3: uart3grp {
355 fsl,pins = <
356 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
357 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
358 >;
359 };
360
361 pinctrl_uart4: uart4grp {
362 fsl,pins = <
363 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
364 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
365 >;
366 };
367
368 pinctrl_usdhc1: usdhc1grp {
369 fsl,pins = <
370 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
371 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
372 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
373 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
374 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
375 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
376 >;
377 };
378
379 pinctrl_usdhc2: usdhc2grp {
380 fsl,pins = <
381 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
382 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
383 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
384 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
385 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
386 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
387 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
388 >;
389 };
390
391 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
392 fsl,pins = <
393 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
394 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
395 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
396 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
397 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
398 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
399 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
400 >;
401 };
402
403 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
404 fsl,pins = <
405 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
406 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
407 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
408 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
409 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
410 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
411 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
412 >;
413 };
414
415 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
416 fsl,pins = <
417 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
418 >;
419 };
420
421 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
422 fsl,pins = <
423 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
424 >;
425 };
426 };
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