1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright 2019-2021 TQ-Systems GmbH
4 */
5
6 /dts-v1/;
7
8 #include "imx8mq-tqma8mq.dtsi"
9 #include "mba8mx.dtsi"
10
11 / {
12 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
13 compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
14 chassis-type = "embedded";
15
16 aliases {
17 eeprom0 = &eeprom3;
18 mmc0 = &usdhc1;
19 mmc1 = &usdhc2;
20 rtc0 = &pcf85063;
21 rtc1 = &snvs_rtc;
22 };
23
24 extcon_usbotg: extcon-usbotg0 {
25 compatible = "linux,extcon-usb-gpio";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_usbcon0>;
28 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
29 };
30
31 reg_otg_vbus: regulator-otg-vbus {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_regotgvbus>;
35 regulator-name = "MBA8MQ_OTG_VBUS";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 reg_usdhc2_vmmc: regulator-vmmc {
43 compatible = "regulator-fixed";
44 regulator-name = "VSD_3V3";
45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>;
47 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
48 enable-active-high;
49 };
50 };
51
52 &btn2 {
53 gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
54 };
55
56 &gpio_leds {
57 led3 {
58 label = "led3";
59 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
60 };
61 };
62
63 &i2c1 {
64 expander2: gpio@25 {
65 compatible = "nxp,pca9555";
66 reg = <0x25>;
67 gpio-controller;
68 #gpio-cells = <2>;
69 vcc-supply = <®_vcc_3v3>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_expander>;
72 interrupt-parent = <&gpio1>;
73 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76
77 mpcie-rst-hog {
78 gpio-hog;
79 gpios = <13 0>;
80 output-high;
81 line-name = "MPCIE_RST#";
82 };
83 };
84 };
85
86 &irqsteer {
87 status = "okay";
88 };
89
90 &led2 {
91 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
92 };
93
94 /* PCIe slot on X36 */
95 &pcie0 {
96 reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
97 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
98 <&pcieclk 3>,
99 <&pcieclk 2>,
100 <&clk IMX8MQ_CLK_PCIE1_AUX>;
101 status = "okay";
102 };
103
104 /*
105 * miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as
106 * static gpio hog.
107 */
108 &pcie1 {
109 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
110 <&pcieclk 1>,
111 <&pcieclk 0>,
112 <&clk IMX8MQ_CLK_PCIE2_AUX>;
113 status = "okay";
114 };
115
116 &sai3 {
117 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
118 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
119 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
120 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
121 <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
122 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
123 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
124 };
125
126 &tlv320aic3x04 {
127 clock-names = "mclk";
128 clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
129 };
130
131 &uart1 {
132 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
133 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
134 };
135
136 &uart2 {
137 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
138 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
139 };
140
141 /* console */
142 &uart3 {
143 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
144 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
145 };
146
147 &usb3_phy0 {
148 vbus-supply = <®_otg_vbus>;
149 status = "okay";
150 };
151
152 &usb_dwc3_0 {
153 /* we implement dual role but not full featured OTG */
154 extcon = <&extcon_usbotg>;
155 hnp-disable;
156 srp-disable;
157 adp-disable;
158 dr_mode = "otg";
159 status = "okay";
160 };
161
162 &usb3_phy1 {
163 vbus-supply = <®_hub_vbus>;
164 status = "okay";
165 };
166
167 &usb_dwc3_1 {
168 status = "okay";
169 dr_mode = "host";
170 };
171
172 &wdog1 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_wdog>;
175 fsl,ext-reset-output;
176 status = "okay";
177 };
178
179 &iomuxc {
180 pinctrl_ecspi1: ecspi1grp {
181 fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0000004e>,
182 <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0000004e>,
183 <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0000004e>,
184 <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0000004e>;
185 };
186
187 pinctrl_ecspi2: ecspi2grp {
188 fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0000004e>,
189 <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0000004e>,
190 <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x0000004e>,
191 <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0000004e>;
192 };
193
194 pinctrl_expander: expandergrp {
195 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0xd6>;
196 };
197
198 pinctrl_fec1: fec1grp {
199 fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
200 <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23>,
201 <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
202 <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
203 <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
204 <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
205 <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
206 <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
207 <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
208 <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
209 <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
210 <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
211 <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
212 <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>;
213 };
214
215 pinctrl_gpiobutton: gpiobuttongrp {
216 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41>,
217 <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41>,
218 <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41>;
219 };
220
221 pinctrl_gpioled: gpioledgrp {
222 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41>,
223 <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41>,
224 <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41>;
225 };
226
227 pinctrl_i2c2: i2c2grp {
228 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067>,
229 <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067>;
230 };
231
232 pinctrl_i2c2_gpio: i2c2gpiogrp {
233 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000067>,
234 <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000067>;
235 };
236
237 pinctrl_i2c3: i2c3grp {
238 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000067>,
239 <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000067>;
240 };
241
242 pinctrl_i2c3_gpio: i2c3gpiogrp {
243 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000067>,
244 <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000067>;
245 };
246
247 pinctrl_pwm3: pwm3grp {
248 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x16>;
249 };
250
251 pinctrl_pwm4: pwm4grp {
252 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16>;
253 };
254
255 pinctrl_regotgvbus: reggotgvbusgrp {
256 /* USB1 OTG PWR as GPIO */
257 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x06>;
258 };
259
260 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
261 fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1>;
262 };
263
264 pinctrl_sai3: sai3grp {
265 fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6>,
266 <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6>,
267 <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6>,
268 <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6>,
269 <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6>,
270 <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6>,
271 <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6>;
272 };
273
274 pinctrl_uart1: uart1grp {
275 fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79>,
276 <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79>;
277 };
278
279 pinctrl_uart2: uart2grp {
280 fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79>,
281 <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79>;
282 };
283
284 pinctrl_uart3: uart3grp {
285 fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79>,
286 <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79>;
287 };
288
289 pinctrl_uart4: uart4grp {
290 fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79>,
291 <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79>;
292 };
293
294 pinctrl_usbcon0: usb0congrp {
295 /* ID: floating / high: device, low: host -> use PU */
296 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xe6>;
297 };
298
299 pinctrl_usdhc2: usdhc2grp {
300 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83>,
301 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3>,
302 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3>,
303 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3>,
304 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3>,
305 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3>,
306 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
307 };
308
309 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
310 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85>,
311 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5>,
312 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5>,
313 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5>,
314 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5>,
315 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5>,
316 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
317 };
318
319 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
320 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f>,
321 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7>,
322 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7>,
323 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7>,
324 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7>,
325 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7>,
326 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
327 };
328
329 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
330 fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41>;
331 };
332 };
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