1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 NXP
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/usb/pd.h>
9 #include "imx93.dtsi"
10
11 / {
12 model = "NXP i.MX93 11X11 EVK board";
13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
14
15 chosen {
16 stdout-path = &lpuart1;
17 };
18
19 reserved-memory {
20 #address-cells = <2>;
21 #size-cells = <2>;
22 ranges;
23
24 linux,cma {
25 compatible = "shared-dma-pool";
26 reusable;
27 alloc-ranges = <0 0x80000000 0 0x40000000>;
28 size = <0 0x10000000>;
29 linux,cma-default;
30 };
31
32 vdev0vring0: vdev0vring0@a4000000 {
33 reg = <0 0xa4000000 0 0x8000>;
34 no-map;
35 };
36
37 vdev0vring1: vdev0vring1@a4008000 {
38 reg = <0 0xa4008000 0 0x8000>;
39 no-map;
40 };
41
42 vdev1vring0: vdev1vring0@a4010000 {
43 reg = <0 0xa4010000 0 0x8000>;
44 no-map;
45 };
46
47 vdev1vring1: vdev1vring1@a4018000 {
48 reg = <0 0xa4018000 0 0x8000>;
49 no-map;
50 };
51
52 rsc_table: rsc-table@2021e000 {
53 reg = <0 0x2021e000 0 0x1000>;
54 no-map;
55 };
56
57 vdevbuffer: vdevbuffer@a4020000 {
58 compatible = "shared-dma-pool";
59 reg = <0 0xa4020000 0 0x100000>;
60 no-map;
61 };
62
63 };
64
65 reg_vdd_12v: regulator-vdd-12v {
66 compatible = "regulator-fixed";
67 regulator-name = "VDD_12V";
68 regulator-min-microvolt = <12000000>;
69 regulator-max-microvolt = <12000000>;
70 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
71 enable-active-high;
72 };
73
74 reg_vref_1v8: regulator-adc-vref {
75 compatible = "regulator-fixed";
76 regulator-name = "vref_1v8";
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <1800000>;
79 };
80
81 reg_usdhc2_vmmc: regulator-usdhc2 {
82 compatible = "regulator-fixed";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
85 regulator-name = "VSD_3V3";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
89 off-on-delay-us = <12000>;
90 enable-active-high;
91 };
92
93 backlight_lvds: backlight-lvds {
94 compatible = "pwm-backlight";
95 pwms = <&adp5585 0 100000 0>;
96 brightness-levels = <0 100>;
97 num-interpolated-steps = <100>;
98 default-brightness-level = <100>;
99 power-supply = <®_vdd_12v>;
100 enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>;
101 status = "disabled";
102 };
103
104 bt_sco_codec: bt-sco-codec {
105 compatible = "linux,bt-sco";
106 #sound-dai-cells = <1>;
107 };
108
109 sound-bt-sco {
110 compatible = "simple-audio-card";
111 simple-audio-card,name = "bt-sco-audio";
112 simple-audio-card,format = "dsp_a";
113 simple-audio-card,bitclock-inversion;
114 simple-audio-card,frame-master = <&btcpu>;
115 simple-audio-card,bitclock-master = <&btcpu>;
116
117 btcpu: simple-audio-card,cpu {
118 sound-dai = <&sai1>;
119 dai-tdm-slot-num = <2>;
120 dai-tdm-slot-width = <16>;
121 };
122
123 simple-audio-card,codec {
124 sound-dai = <&bt_sco_codec 1>;
125 };
126 };
127
128 sound-micfil {
129 compatible = "fsl,imx-audio-card";
130 model = "micfil-audio";
131
132 pri-dai-link {
133 link-name = "micfil hifi";
134 format = "i2s";
135
136 cpu {
137 sound-dai = <&micfil>;
138 };
139 };
140 };
141
142 sound-xcvr {
143 compatible = "fsl,imx-audio-card";
144 model = "imx-audio-xcvr";
145
146 pri-dai-link {
147 link-name = "XCVR PCM";
148
149 cpu {
150 sound-dai = <&xcvr>;
151 };
152 };
153 };
154 };
155
156 &adc1 {
157 vref-supply = <®_vref_1v8>;
158 status = "okay";
159 };
160
161 &cm33 {
162 mbox-names = "tx", "rx", "rxdb";
163 mboxes = <&mu1 0 1>,
164 <&mu1 1 1>,
165 <&mu1 3 1>;
166 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
167 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
168 status = "okay";
169 };
170
171 &eqos {
172 pinctrl-names = "default", "sleep";
173 pinctrl-0 = <&pinctrl_eqos>;
174 pinctrl-1 = <&pinctrl_eqos_sleep>;
175 phy-mode = "rgmii-id";
176 phy-handle = <ðphy1>;
177 status = "okay";
178
179 mdio {
180 compatible = "snps,dwmac-mdio";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 clock-frequency = <5000000>;
184
185 ethphy1: ethernet-phy@1 {
186 reg = <1>;
187 eee-broken-1000t;
188 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
189 reset-assert-us = <10000>;
190 reset-deassert-us = <80000>;
191 };
192 };
193 };
194
195 &fec {
196 pinctrl-names = "default", "sleep";
197 pinctrl-0 = <&pinctrl_fec>;
198 pinctrl-1 = <&pinctrl_fec_sleep>;
199 phy-mode = "rgmii-id";
200 phy-handle = <ðphy2>;
201 fsl,magic-packet;
202 status = "okay";
203
204 mdio {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 clock-frequency = <5000000>;
208
209 ethphy2: ethernet-phy@2 {
210 reg = <2>;
211 eee-broken-1000t;
212 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
213 reset-assert-us = <10000>;
214 reset-deassert-us = <80000>;
215 };
216 };
217 };
218
219 &lpi2c1 {
220 clock-frequency = <400000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_lpi2c1>;
223 status = "okay";
224
225 inertial-meter@6a {
226 compatible = "st,lsm6dso";
227 reg = <0x6a>;
228 };
229 };
230
231 &lpi2c2 {
232 clock-frequency = <400000>;
233 pinctrl-names = "default", "sleep";
234 pinctrl-0 = <&pinctrl_lpi2c2>;
235 pinctrl-1 = <&pinctrl_lpi2c2>;
236 status = "okay";
237
238 pcal6524: gpio@22 {
239 compatible = "nxp,pcal6524";
240 reg = <0x22>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pcal6524>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 interrupt-parent = <&gpio3>;
248 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
249 };
250
251 pmic@25 {
252 compatible = "nxp,pca9451a";
253 reg = <0x25>;
254 interrupt-parent = <&pcal6524>;
255 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
256
257 regulators {
258 buck1: BUCK1 {
259 regulator-name = "BUCK1";
260 regulator-min-microvolt = <610000>;
261 regulator-max-microvolt = <950000>;
262 regulator-boot-on;
263 regulator-always-on;
264 regulator-ramp-delay = <3125>;
265 };
266
267 buck2: BUCK2 {
268 regulator-name = "BUCK2";
269 regulator-min-microvolt = <600000>;
270 regulator-max-microvolt = <670000>;
271 regulator-boot-on;
272 regulator-always-on;
273 regulator-ramp-delay = <3125>;
274 };
275
276 buck4: BUCK4{
277 regulator-name = "BUCK4";
278 regulator-min-microvolt = <1620000>;
279 regulator-max-microvolt = <3400000>;
280 regulator-boot-on;
281 regulator-always-on;
282 };
283
284 buck5: BUCK5{
285 regulator-name = "BUCK5";
286 regulator-min-microvolt = <1620000>;
287 regulator-max-microvolt = <3400000>;
288 regulator-boot-on;
289 regulator-always-on;
290 };
291
292 buck6: BUCK6 {
293 regulator-name = "BUCK6";
294 regulator-min-microvolt = <1060000>;
295 regulator-max-microvolt = <1140000>;
296 regulator-boot-on;
297 regulator-always-on;
298 };
299
300 ldo1: LDO1 {
301 regulator-name = "LDO1";
302 regulator-min-microvolt = <1620000>;
303 regulator-max-microvolt = <1980000>;
304 regulator-boot-on;
305 regulator-always-on;
306 };
307
308 ldo4: LDO4 {
309 regulator-name = "LDO4";
310 regulator-min-microvolt = <800000>;
311 regulator-max-microvolt = <840000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
315
316 ldo5: LDO5 {
317 regulator-name = "LDO5";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-boot-on;
321 regulator-always-on;
322 };
323 };
324 };
325
326 adp5585: io-expander@34 {
327 compatible = "adi,adp5585-00", "adi,adp5585";
328 reg = <0x34>;
329 vdd-supply = <&buck4>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 gpio-reserved-ranges = <5 1>;
333 #pwm-cells = <3>;
334 };
335 };
336
337 &lpi2c3 {
338 clock-frequency = <400000>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_lpi2c3>;
341 status = "okay";
342
343 ptn5110: tcpc@50 {
344 compatible = "nxp,ptn5110", "tcpci";
345 reg = <0x50>;
346 interrupt-parent = <&gpio3>;
347 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
348
349 typec1_con: connector {
350 compatible = "usb-c-connector";
351 label = "USB-C";
352 power-role = "dual";
353 data-role = "dual";
354 try-power-role = "sink";
355 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
356 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
357 PDO_VAR(5000, 20000, 3000)>;
358 op-sink-microwatt = <15000000>;
359 self-powered;
360
361 ports {
362 #address-cells = <1>;
363 #size-cells = <0>;
364
365 port@0 {
366 reg = <0>;
367
368 typec1_dr_sw: endpoint {
369 remote-endpoint = <&usb1_drd_sw>;
370 };
371 };
372 };
373 };
374 };
375
376 ptn5110_2: tcpc@51 {
377 compatible = "nxp,ptn5110", "tcpci";
378 reg = <0x51>;
379 interrupt-parent = <&gpio3>;
380 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
381
382 typec2_con: connector {
383 compatible = "usb-c-connector";
384 label = "USB-C";
385 power-role = "dual";
386 data-role = "dual";
387 try-power-role = "sink";
388 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
389 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
390 PDO_VAR(5000, 20000, 3000)>;
391 op-sink-microwatt = <15000000>;
392 self-powered;
393
394 ports {
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 port@0 {
399 reg = <0>;
400
401 typec2_dr_sw: endpoint {
402 remote-endpoint = <&usb2_drd_sw>;
403 };
404 };
405 };
406 };
407 };
408
409 pcf2131: rtc@53 {
410 compatible = "nxp,pcf2131";
411 reg = <0x53>;
412 interrupt-parent = <&pcal6524>;
413 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
414 };
415 };
416
417 &lpuart1 { /* console */
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_uart1>;
420 status = "okay";
421 };
422
423 &lpuart5 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart5>;
426 status = "okay";
427 };
428
429 &micfil {
430 pinctrl-names = "default", "sleep";
431 pinctrl-0 = <&pinctrl_pdm>;
432 pinctrl-1 = <&pinctrl_pdm_sleep>;
433 assigned-clocks = <&clk IMX93_CLK_PDM>;
434 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
435 assigned-clock-rates = <49152000>;
436 status = "okay";
437 };
438
439 &mu1 {
440 status = "okay";
441 };
442
443 &mu2 {
444 status = "okay";
445 };
446
447 &sai1 {
448 pinctrl-names = "default", "sleep";
449 pinctrl-0 = <&pinctrl_sai1>;
450 pinctrl-1 = <&pinctrl_sai1_sleep>;
451 assigned-clocks = <&clk IMX93_CLK_SAI1>;
452 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
453 assigned-clock-rates = <12288000>;
454 fsl,sai-mclk-direction-output;
455 status = "okay";
456 };
457
458 &usbotg1 {
459 dr_mode = "otg";
460 hnp-disable;
461 srp-disable;
462 adp-disable;
463 usb-role-switch;
464 disable-over-current;
465 samsung,picophy-pre-emp-curr-control = <3>;
466 samsung,picophy-dc-vol-level-adjust = <7>;
467 status = "okay";
468
469 port {
470 usb1_drd_sw: endpoint {
471 remote-endpoint = <&typec1_dr_sw>;
472 };
473 };
474 };
475
476 &usbotg2 {
477 dr_mode = "otg";
478 hnp-disable;
479 srp-disable;
480 adp-disable;
481 usb-role-switch;
482 disable-over-current;
483 samsung,picophy-pre-emp-curr-control = <3>;
484 samsung,picophy-dc-vol-level-adjust = <7>;
485 status = "okay";
486
487 port {
488 usb2_drd_sw: endpoint {
489 remote-endpoint = <&typec2_dr_sw>;
490 };
491 };
492 };
493
494 &usdhc1 {
495 pinctrl-names = "default", "state_100mhz", "state_200mhz";
496 pinctrl-0 = <&pinctrl_usdhc1>;
497 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
498 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
499 bus-width = <8>;
500 non-removable;
501 status = "okay";
502 };
503
504 &usdhc2 {
505 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
506 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
509 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
510 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
511 vmmc-supply = <®_usdhc2_vmmc>;
512 bus-width = <4>;
513 status = "okay";
514 no-mmc;
515 };
516
517 &wdog3 {
518 status = "okay";
519 };
520
521 &xcvr {
522 pinctrl-names = "default", "sleep";
523 pinctrl-0 = <&pinctrl_spdif>;
524 pinctrl-1 = <&pinctrl_spdif_sleep>;
525 assigned-clocks = <&clk IMX93_CLK_SPDIF>,
526 <&clk IMX93_CLK_AUDIO_XCVR>;
527 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>,
528 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
529 assigned-clock-rates = <12288000>, <200000000>;
530 status = "okay";
531 };
532
533 &iomuxc {
534 pinctrl_eqos: eqosgrp {
535 fsl,pins = <
536 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
537 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
538 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
539 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
540 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
541 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
542 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
543 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
544 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
545 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
546 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
547 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
548 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
549 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
550 >;
551 };
552
553 pinctrl_eqos_sleep: eqossleepgrp {
554 fsl,pins = <
555 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
556 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
557 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
558 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
559 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
560 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
561 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
562 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
563 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
564 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
565 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
566 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
567 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
568 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
569 >;
570 };
571
572 pinctrl_fec: fecgrp {
573 fsl,pins = <
574 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
575 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
576 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
577 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
578 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
579 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
580 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
581 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
582 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
583 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
584 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
585 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
586 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
587 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
588 >;
589 };
590
591 pinctrl_lpi2c3: lpi2c3grp {
592 fsl,pins = <
593 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
594 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
595 >;
596 };
597
598 pinctrl_fec_sleep: fecsleepgrp {
599 fsl,pins = <
600 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
601 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
602 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
603 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
604 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
605 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
606 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
607 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
608 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
609 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
610 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
611 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
612 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
613 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
614 >;
615 };
616
617 pinctrl_uart1: uart1grp {
618 fsl,pins = <
619 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
620 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
621 >;
622 };
623
624 pinctrl_uart5: uart5grp {
625 fsl,pins = <
626 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
627 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
628 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
629 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
630 >;
631 };
632
633 pinctrl_lpi2c1: lpi2c1grp {
634 fsl,pins = <
635 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
636 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
637 >;
638 };
639
640 pinctrl_lpi2c2: lpi2c2grp {
641 fsl,pins = <
642 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
643 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
644 >;
645 };
646
647 pinctrl_lpi2c3: lpi2c3grp {
648 fsl,pins = <
649 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
650 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
651 >;
652 };
653
654 pinctrl_pcal6524: pcal6524grp {
655 fsl,pins = <
656 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
657 >;
658 };
659
660 pinctrl_pdm: pdmgrp {
661 fsl,pins = <
662 MX93_PAD_PDM_CLK__PDM_CLK 0x31e
663 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e
664 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e
665 >;
666 };
667
668 pinctrl_pdm_sleep: pdmsleepgrp {
669 fsl,pins = <
670 MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e
671 MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e
672 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
673 >;
674 };
675
676 pinctrl_sai1: sai1grp {
677 fsl,pins = <
678 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
679 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
680 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
681 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
682 >;
683 };
684
685 pinctrl_sai1_sleep: sai1sleepgrp {
686 fsl,pins = <
687 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e
688 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
689 MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
690 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
691 >;
692 };
693
694 /* need to config the SION for data and cmd pad, refer to ERR052021 */
695 pinctrl_usdhc1: usdhc1grp {
696 fsl,pins = <
697 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
698 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
699 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
700 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
701 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
702 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
703 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
704 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
705 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
706 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
707 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
708 >;
709 };
710
711 /* need to config the SION for data and cmd pad, refer to ERR052021 */
712 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
713 fsl,pins = <
714 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
715 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
716 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
717 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
718 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
719 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
720 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
721 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
722 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
723 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
724 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
725 >;
726 };
727
728 /* need to config the SION for data and cmd pad, refer to ERR052021 */
729 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
730 fsl,pins = <
731 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
732 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
733 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
734 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
735 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
736 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
737 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
738 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
739 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
740 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
741 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
742 >;
743 };
744
745 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
746 fsl,pins = <
747 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
748 >;
749 };
750
751 pinctrl_spdif: spdifgrp {
752 fsl,pins = <
753 MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e
754 MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e
755 >;
756 };
757
758 pinctrl_spdif_sleep: spdifsleepgrp {
759 fsl,pins = <
760 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
761 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
762 >;
763 };
764
765 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
766 fsl,pins = <
767 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
768 >;
769 };
770
771 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
772 fsl,pins = <
773 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
774 >;
775 };
776
777 /* need to config the SION for data and cmd pad, refer to ERR052021 */
778 pinctrl_usdhc2: usdhc2grp {
779 fsl,pins = <
780 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
781 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
782 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
783 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
784 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
785 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
786 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
787 >;
788 };
789
790 /* need to config the SION for data and cmd pad, refer to ERR052021 */
791 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
792 fsl,pins = <
793 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
794 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
795 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
796 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
797 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
798 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
799 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
800 >;
801 };
802
803 /* need to config the SION for data and cmd pad, refer to ERR052021 */
804 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
805 fsl,pins = <
806 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
807 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
808 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
809 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
810 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
811 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
812 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
813 >;
814 };
815
816 pinctrl_usdhc2_sleep: usdhc2sleepgrp {
817 fsl,pins = <
818 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
819 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
820 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
821 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
822 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
823 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
824 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
825 >;
826 };
827
828 };
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