1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2024 Kontron Electronics GmbH
4 */
5
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "imx93.dtsi"
8
9 / {
10 model = "Kontron OSM-S i.MX93";
11 compatible = "kontron,imx93-osm-s", "fsl,imx93";
12
13 aliases {
14 rtc0 = &rv3028;
15 rtc1 = &bbnsm_rtc;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x80000000>;
21 };
22
23 chosen {
24 stdout-path = &lpuart1;
25 };
26
27 reg_usdhc2_vcc: regulator-usdhc2-vcc {
28 compatible = "regulator-fixed";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
31 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-name = "VCC_SDIO_A";
36 };
37
38 reg_vdd_carrier: regulator-vdd-carrier {
39 compatible = "regulator-fixed";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
42 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
43 enable-active-high;
44 regulator-always-on;
45 regulator-boot-on;
46 regulator-name = "VDD_CARRIER";
47
48 regulator-state-standby {
49 regulator-on-in-suspend;
50 };
51
52 regulator-state-mem {
53 regulator-off-in-suspend;
54 };
55
56 regulator-state-disk {
57 regulator-off-in-suspend;
58 };
59 };
60 };
61
62 &flexcan1 { /* OSM-S CAN_A */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_flexcan1>;
65 };
66
67 &flexcan2 { /* OSM-S CAN_B */
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan2>;
70 };
71
72 &gpio1 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio1>;
75 gpio-line-names = "", "", "I2C_A_SCL", "I2C_A_SDA",
76 "UART_CON_RX", "UART_CON_TX", "UART_C_RX", "UART_C_TX",
77 "CAN_A_TX", "CAN_A_RX", "GPIO_A_0", "SPI_A_CS0",
78 "SPI_A_SDI", "SPI_A_SCK","SPI_A_SDO";
79 };
80
81 &gpio2 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_gpio2>;
84 gpio-line-names = "I2C_B_SDA", "I2C_B_SCL", "GPIO_B_1", "GPIO_A_2",
85 "UART_B_TX", "UART_B_RX", "UART_B_RTS", "UART_B_CTS",
86 "UART_A_TX", "UART_A_RX", "UART_A_RTS", "UART_A_CTS",
87 "SPI_B_CS0", "SPI_B_SDI", "SPI_B_SDO", "SPI_B_SCK",
88 "I2S_BITCLK", "I2S_MCLK", "GPIO_A_1", "I2S_A_DATA_OUT",
89 "I2S_A_DATA_IN", "PWM_2", "GPIO_A_3", "PWM_1",
90 "PWM_0", "CAN_B_TX", "I2S_LRCLK", "CAN_B_RX", "GPIO_A_4",
91 "GPIO_A_5";
92 };
93
94 &gpio3 {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_gpio3>;
97 gpio-line-names = "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
98 "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",
99 "", "", "", "",
100 "", "", "", "",
101 "", "", "", "",
102 "SDIO_B_CLK", "SDIO_B_CMD", "SDIO_B_D0", "SDIO_B_D1",
103 "SDIO_B_D2", "SDIO_B_D3", "GPIO_A_6", "GPIO_A_7";
104 };
105
106 &gpio4 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_gpio4>;
109 gpio-line-names = "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD4", "ETH_B_TXD3",
110 "ETH_B_TXD2", "ETH_B_TXD1", "ETH_B_TX_EN", "ETH_B_TX_CLK",
111 "ETH_B_RX_CTL", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",
112 "ETH_B_RXD2", "ETH_B_RXD3", "ETH_MDC", "ETH_MDIO",
113 "ETH_A_TXD3", "ETH_A_TXD2", "ETH_A_TXD1", "ETH_A_TXD0",
114 "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH_A_RX_CTL", "ETH_A_RX_CLK",
115 "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3",
116 "GPIO_B_0", "CARRIER_PWR_EN";
117 };
118
119 &lpi2c1 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_lpi2c1>;
122 status = "okay";
123
124 pca9451: pmic@25 {
125 compatible = "nxp,pca9451a";
126 reg = <0x25>;
127 nxp,i2c-lt-enable;
128
129 regulators {
130 reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */
131 regulator-name = "+0V8_VDD_SOC (BUCK1)";
132 regulator-min-microvolt = <650000>;
133 regulator-max-microvolt = <950000>;
134 regulator-boot-on;
135 regulator-always-on;
136 regulator-ramp-delay = <3125>;
137 };
138
139 reg_vddq_ddr: BUCK2 {
140 regulator-name = "+0V6_VDDQ_DDR (BUCK2)";
141 regulator-min-microvolt = <600000>;
142 regulator-max-microvolt = <600000>;
143 regulator-boot-on;
144 regulator-always-on;
145 regulator-ramp-delay = <3125>;
146 };
147
148 reg_vdd_3v3: BUCK4 {
149 regulator-name = "+3V3 (BUCK4)";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-boot-on;
153 regulator-always-on;
154 };
155
156 reg_vdd_1v8: BUCK5 {
157 regulator-name = "+1V8 (BUCK5)";
158 regulator-min-microvolt = <1800000>;
159 regulator-max-microvolt = <1800000>;
160 regulator-boot-on;
161 regulator-always-on;
162 };
163
164 reg_nvcc_dram: BUCK6 {
165 regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
166 regulator-min-microvolt = <1100000>;
167 regulator-max-microvolt = <1100000>;
168 regulator-boot-on;
169 regulator-always-on;
170 };
171
172 reg_nvcc_snvs: LDO1 {
173 regulator-name = "+1V8_NVCC_SNVS (LDO1)";
174 regulator-min-microvolt = <1800000>;
175 regulator-max-microvolt = <1800000>;
176 regulator-boot-on;
177 regulator-always-on;
178 };
179
180 reg_vdd_ana: LDO4 {
181 regulator-name = "+0V8_VDD_ANA (LDO4)";
182 regulator-min-microvolt = <800000>;
183 regulator-max-microvolt = <800000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 reg_nvcc_sd: LDO5 {
189 regulator-name = "NVCC_SD (LDO5)";
190 regulator-min-microvolt = <1800000>;
191 regulator-max-microvolt = <3300000>;
192 };
193 };
194 };
195
196 eeprom@50 {
197 compatible = "onnn,n24s64b", "atmel,24c64";
198 reg = <0x50>;
199 pagesize = <32>;
200 size = <8192>;
201 num-addresses = <1>;
202 };
203
204 rv3028: rtc@52 {
205 compatible = "microcrystal,rv3028";
206 reg = <0x52>;
207 };
208 };
209
210 &lpi2c2 { /* OSM-S I2C_A */
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_lpi2c2>;
213 };
214
215 &lpi2c3 { /* OSM-S I2C_B */
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_lpi2c3>;
218 };
219
220 &lpspi1 { /* OSM-S SPI_A */
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_lpspi1>;
223 cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
224 };
225
226 &lpspi8 { /* OSM-S SPI_B */
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_lpspi8>;
229 cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
230 };
231
232 &lpuart1 { /* OSM-S UART_CON */
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_lpuart1>;
235 };
236
237 &lpuart2 { /* OSM-S UART_C */
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_lpuart2>;
240 };
241
242 &lpuart6 { /* OSM-S UART_B */
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_lpuart6>;
245 };
246
247 &lpuart7 { /* OSM-S UART_A */
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_lpuart7>;
250 };
251
252 &tpm3 { /* OSM-S PWM_0 */
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_tpm3>;
255 };
256
257 &tpm4 { /* OSM-S PWM_2 */
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_tpm4>;
260 };
261
262 &tpm6 { /* OSM-S PWM_1 */
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_tpm6>;
265 };
266
267 &usdhc1 { /* eMMC */
268 pinctrl-names = "default", "state_100mhz", "state_200mhz";
269 pinctrl-0 = <&pinctrl_usdhc1>;
270 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
271 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
272 vmmc-supply = <®_vdd_3v3>;
273 vqmmc-supply = <®_vdd_1v8>;
274 bus-width = <8>;
275 non-removable;
276 status = "okay";
277 };
278
279 &usdhc2 { /* OSM-S SDIO_A */
280 pinctrl-names = "default", "state_100mhz", "state_200mhz";
281 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
282 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
283 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
284 vmmc-supply = <®_usdhc2_vcc>;
285 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
286 };
287
288 &usdhc3 { /* OSM-S SDIO_B */
289 pinctrl-names = "default", "state_100mhz", "state_200mhz";
290 pinctrl-0 = <&pinctrl_usdhc3>;
291 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
292 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
293 vqmmc-supply = <®_vdd_1v8>;
294 };
295
296 &wdog3 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_wdog>;
299 fsl,ext-reset-output;
300 status = "okay";
301 };
302
303 &iomuxc {
304 pinctrl_enet_rgmii: enetrgmiigrp {
305 fsl,pins = <
306 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e /* ETH_MDC */
307 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e /* ETH_MDIO */
308 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e /* ETH_A_(S)(R)(G)MII_RXD0 */
309 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e /* ETH_A_(S)(R)(G)MII_RXD1 */
310 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e /* ETH_A_(R)(G)MII_RXD2 */
311 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e /* ETH_A_(R)(G)MII_RXD3 */
312 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe /* ETH_A_(R)(G)MII_RX_CLK */
313 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e /* ETH_A_(R)(G)MII_RX_DV(_ER) */
314 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e /* ETH_A_(S)(R)(G)MII_TXD0 */
315 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e /* ETH_A_(S)(R)(G)MII_TXD1 */
316 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e /* ETH_A_(S)(R)(G)MII_TXD2 */
317 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e /* ETH_A_(S)(R)(G)MII_TXD3 */
318 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe /* ETH_A_(R)(G)MII_TX_CLK */
319 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e /* ETH_A_(R)(G)MII_TX_EN(_ER) */
320 >;
321 };
322
323 pinctrl_eqos_rgmii: eqosrgmiigrp {
324 fsl,pins = <
325 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e /* ETH_B_MDC */
326 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e /* ETH_B_MDIO */
327 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e /* ETH_B_(S)(R)(G)MII_RXD0 */
328 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e /* ETH_B_(S)(R)(G)MII_RXD1 */
329 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e /* ETH_B_(R)(G)MII_RXD2 */
330 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e /* ETH_B_(R)(G)MII_RXD3 */
331 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x57e /* ETH_B_(R)(G)MII_RX_CLK */
332 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e /* ETH_B_(R)(G)MII_RX_DV(_ER) */
333 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e /* ETH_B_(S)(R)(G)MII_TXD0 */
334 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e /* ETH_B_(S)(R)(G)MII_TXD1 */
335 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e /* ETH_B_(S)(R)(G)MII_TXD2 */
336 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e /* ETH_B_(S)(R)(G)MII_TXD3 */
337 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x57e /* ETH_B_(R)(G)MII_TX_CLK */
338 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e /* ETH_B_(R)(G)MII_TX_EN(_ER) */
339 >;
340 };
341
342 pinctrl_flexcan1: flexcan1grp {
343 fsl,pins = <
344 MX93_PAD_PDM_CLK__CAN1_TX 0x139e /* CAN_A_TX */
345 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e /* CAN_A_RX */
346 >;
347 };
348
349 pinctrl_flexcan2: flexcan2grp {
350 fsl,pins = <
351 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e /* CAN_B_TX */
352 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e /* CAN_B_RX */
353 >;
354 };
355
356 pinctrl_gpio1: gpio1grp {
357 fsl,pins = <
358 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e /* GPIO_A_0 */
359 >;
360 };
361
362 pinctrl_gpio2: gpio2grp {
363 fsl,pins = <
364 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e /* GPIO_A_1 */
365 MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e /* GPIO_A_2 */
366 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* GPIO_A_3 */
367 MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e /* GPIO_A_4 */
368 MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e /* GPIO_A_5 */
369 MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e /* GPIO_B_1 */
370 >;
371 };
372
373 pinctrl_gpio3: gpio3grp {
374 fsl,pins = <
375 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e /* GPIO_A_6 */
376 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* GPIO_A_7 */
377 >;
378 };
379
380 pinctrl_gpio4: gpio4grp {
381 fsl,pins = <
382 MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* GPIO_B_0 */
383 >;
384 };
385
386 pinctrl_lpi2c1: lpi2c1grp {
387 fsl,pins = <
388 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
389 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
390 >;
391 };
392
393 pinctrl_lpi2c2: lpi2c2grp {
394 fsl,pins = <
395 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e /* I2C_A_SCL */
396 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e /* I2C_A_SDA */
397 >;
398 };
399
400 pinctrl_lpi2c3: lpi2c3grp {
401 fsl,pins = <
402 MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e /* I2C_B_SCL */
403 MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e /* I2C_B_SDA */
404 >;
405 };
406
407 pinctrl_lpspi1: lpspi1grp {
408 fsl,pins = <
409 MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x3fe /* SPI_A_SDI_(IO0) */
410 MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x3fe /* SPI_A_SDO_(IO1) */
411 MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x3fe /* SPI_A_SCK */
412 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x3fe /* SPI_A_CS0# */
413 >;
414 };
415
416 pinctrl_lpspi8: lpspi8grp {
417 fsl,pins = <
418 MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x3fe /* SPI_B_SDI */
419 MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x3fe /* SPI_B_SDO */
420 MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x3fe /* SPI_B_SCK */
421 MX93_PAD_GPIO_IO12__GPIO2_IO12 0x3fe /* SPI_B_CS0# */
422 >;
423 };
424
425 pinctrl_lpuart1: lpuart1grp {
426 fsl,pins = <
427 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e /* UART_CON_RX */
428 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e /* UART_CON_TX */
429 >;
430 };
431
432 pinctrl_lpuart2: lpuart2grp {
433 fsl,pins = <
434 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e /* UART_C_RX */
435 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e /* UART_C_TX */
436 >;
437 };
438
439 pinctrl_lpuart6: lpuart6grp {
440 fsl,pins = <
441 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e /* UART_B_RX */
442 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e /* UART_B_TX */
443 MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e /* UART_B_CTS */
444 MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e /* UART_B_RTS */
445 >;
446 };
447
448 pinctrl_lpuart7: lpuart7grp {
449 fsl,pins = <
450 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e /* UART_A_RX */
451 MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e /* UART_A_TX */
452 MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e /* UART_A_CTS */
453 MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e /* UART_A_RTS */
454 >;
455 };
456
457 pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {
458 fsl,pins = <
459 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e /* SDIO_A_PWR_EN */
460 >;
461 };
462
463 pinctrl_reg_vdd_carrier: regvddcarriergrp {
464 fsl,pins = <
465 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* CARRIER_PWR_EN */
466 >;
467 };
468
469 pinctrl_sai3: sai3grp {
470 fsl,pins = <
471 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */
472 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e /* I2S_A_DATA_OUT */
473 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e /* I2S_MCLK */
474 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e /* I2S_LRCLK */
475 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e /* I2S_BITCLK */
476 >;
477 };
478
479 pinctrl_tpm3: tpm3grp {
480 fsl,pins = <
481 MX93_PAD_GPIO_IO24__TPM3_CH3 0x57e /* PWM_0 */
482 >;
483 };
484
485 pinctrl_tpm4: tpm4grp {
486 fsl,pins = <
487 MX93_PAD_GPIO_IO21__TPM4_CH1 0x57e /* PWM_2 */
488 >;
489 };
490
491 pinctrl_tpm6: tpm6grp {
492 fsl,pins = <
493 MX93_PAD_GPIO_IO23__TPM6_CH1 0x57e /* PWM_1 */
494 >;
495 };
496
497 /* need to config the SION for data and cmd pad, refer to ERR052021 */
498 pinctrl_usdhc1: usdhc1grp {
499 fsl,pins = <
500 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
501 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
502 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
503 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
504 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
505 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
506 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
507 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
508 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
509 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
510 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
511 >;
512 };
513
514 /* need to config the SION for data and cmd pad, refer to ERR052021 */
515 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
516 fsl,pins = <
517 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
518 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
519 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
520 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
521 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
522 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
523 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
524 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
525 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
526 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
527 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
528 >;
529 };
530
531 /* need to config the SION for data and cmd pad, refer to ERR052021 */
532 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
533 fsl,pins = <
534 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
535 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
536 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
537 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
538 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
539 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
540 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
541 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
542 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
543 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
544 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
545 >;
546 };
547
548 pinctrl_usdhc2: usdhc2grp {
549 fsl,pins = <
550 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 /* SDIO_A_CLK */
551 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 /* SDIO_A_CMD */
552 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 /* SDIO_A_D0 */
553 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */
554 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */
555 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */
556 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0
557 >;
558 };
559
560 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
561 fsl,pins = <
562 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e /* SDIO_A_CLK */
563 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e /* SDIO_A_CMD */
564 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e /* SDIO_A_D0 */
565 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */
566 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */
567 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */
568 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0
569 >;
570 };
571
572 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
573 fsl,pins = <
574 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* SDIO_A_CLK */
575 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe /* SDIO_A_CMD */
576 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe /* SDIO_A_D0 */
577 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */
578 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */
579 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */
580 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0
581 >;
582 };
583
584 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
585 fsl,pins = <
586 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e /* SDIO_A_CD# */
587 >;
588 };
589
590 pinctrl_usdhc3: usdhc3grp {
591 fsl,pins = <
592 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 /* SDIO_B_CLK */
593 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 /* SDIO_B_CMD */
594 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 /* SDIO_B_D0 */
595 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 /* SDIO_B_D1 */
596 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 /* SDIO_B_D2 */
597 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 /* SDIO_B_D3 */
598 >;
599 };
600
601 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
602 fsl,pins = <
603 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e /* SDIO_B_CLK */
604 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e /* SDIO_B_CMD */
605 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e /* SDIO_B_D0 */
606 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e /* SDIO_B_D1 */
607 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e /* SDIO_B_D2 */
608 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e /* SDIO_B_D3 */
609 >;
610 };
611
612 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
613 fsl,pins = <
614 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe /* SDIO_B_CLK */
615 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe /* SDIO_B_CMD */
616 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe /* SDIO_B_D0 */
617 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe /* SDIO_B_D1 */
618 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe /* SDIO_B_D2 */
619 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe /* SDIO_B_D3 */
620 >;
621 };
622
623 pinctrl_wdog: wdoggrp {
624 fsl,pins = <
625 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0xc6
626 >;
627 };
628 };
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