1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8 /dts-v1/;
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "imx93-tqma9352.dtsi"
16
17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
19 compatible = "tq,imx93-tqma9352-mba93xxla",
20 "tq,imx93-tqma9352", "fsl,imx93";
21 chassis-type = "embedded";
22
23 chosen {
24 stdout-path = &lpuart1;
25 };
26
27 aliases {
28 eeprom0 = &eeprom0;
29 ethernet0 = &fec;
30 ethernet1 = &eqos;
31 rtc0 = &pcf85063;
32 rtc1 = &bbnsm_rtc;
33 };
34
35 backlight_lvds: backlight {
36 compatible = "pwm-backlight";
37 pwms = <&tpm5 0 5000000 0>;
38 brightness-levels = <0 4 8 16 32 64 128 255>;
39 default-brightness-level = <7>;
40 power-supply = <®_12v0>;
41 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
42 status = "disabled";
43 };
44
45 clk_dp: clk-dp {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <26000000>;
49 };
50
51 gpio-keys {
52 compatible = "gpio-keys";
53 autorepeat;
54
55 switch-a {
56 label = "switcha";
57 linux,code = <BTN_0>;
58 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
59 wakeup-source;
60 };
61
62 switch-b {
63 label = "switchb";
64 linux,code = <BTN_1>;
65 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
66 wakeup-source;
67 };
68 };
69
70 gpio-leds {
71 compatible = "gpio-leds";
72
73 led-1 {
74 color = <LED_COLOR_ID_GREEN>;
75 function = LED_FUNCTION_STATUS;
76 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "default-on";
78 };
79
80 led-2 {
81 color = <LED_COLOR_ID_AMBER>;
82 function = LED_FUNCTION_HEARTBEAT;
83 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
84 linux,default-trigger = "heartbeat";
85 };
86 };
87
88 iio-hwmon {
89 compatible = "iio-hwmon";
90 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
91 };
92
93 reg_3v3: regulator-3v3 {
94 compatible = "regulator-fixed";
95 regulator-name = "V_3V3_MB";
96 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <3300000>;
98 };
99
100 reg_3v8: regulator-3v8 {
101 compatible = "regulator-fixed";
102 regulator-name = "V_3V8";
103 regulator-min-microvolt = <3800000>;
104 regulator-max-microvolt = <3800000>;
105 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 /* TODO: this is supply for IOT module */
108 regulator-always-on;
109 };
110
111 reg_5v0: regulator-5v0 {
112 compatible = "regulator-fixed";
113 regulator-name = "V_5V0_MB";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
116 };
117
118 reg_12v0: regulator-12v0 {
119 compatible = "regulator-fixed";
120 regulator-name = "V_12V";
121 regulator-min-microvolt = <12000000>;
122 regulator-max-microvolt = <12000000>;
123 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
124 enable-active-high;
125 };
126 };
127
128 &adc1 {
129 status = "okay";
130 };
131
132 &eqos {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id";
136 phy-handle = <ðphy_eqos>;
137 status = "okay";
138
139 mdio {
140 compatible = "snps,dwmac-mdio";
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 ethphy_eqos: ethernet-phy@0 {
145 compatible = "ethernet-phy-ieee802.3-c22";
146 reg = <0>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_eqos_phy>;
149 interrupt-parent = <&gpio3>;
150 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
151 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
152 reset-assert-us = <500000>;
153 reset-deassert-us = <50000>;
154 enet-phy-lane-no-swap;
155 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
156 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
157 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
158 ti,dp83867-rxctrl-strap-quirk;
159 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
160 };
161 };
162 };
163
164 &fec {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec>;
167 phy-mode = "rgmii-id";
168 phy-handle = <ðphy_fec>;
169 fsl,magic-packet;
170 status = "okay";
171
172 mdio {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-frequency = <5000000>;
176
177 ethphy_fec: ethernet-phy@0 {
178 compatible = "ethernet-phy-ieee802.3-c22";
179 reg = <0>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_fec_phy>;
182 interrupt-parent = <&gpio3>;
183 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
184 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
185 reset-assert-us = <500000>;
186 reset-deassert-us = <50000>;
187 enet-phy-lane-no-swap;
188 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
189 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
190 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
191 ti,dp83867-rxctrl-strap-quirk;
192 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
193 };
194 };
195 };
196
197 &flexcan1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_flexcan1>;
200 xceiver-supply = <®_3v3>;
201 status = "okay";
202 };
203
204 &flexcan2 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_flexcan2>;
207 xceiver-supply = <®_3v3>;
208 status = "okay";
209 };
210
211 &gpio1 {
212 gpio-line-names =
213 /* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
214 /* 04 */ "", "", "", "",
215 /* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
216 /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
217 /* 16 */ "", "", "", "",
218 /* 20 */ "", "", "", "",
219 /* 24 */ "", "", "", "",
220 /* 28 */ "", "", "", "";
221
222 expander-irq-hog {
223 gpio-hog;
224 gpios = <12 GPIO_ACTIVE_LOW>;
225 input;
226 line-name = "PEX_INT#";
227 };
228
229 rtc-irq-hog {
230 gpio-hog;
231 gpios = <14 GPIO_ACTIVE_LOW>;
232 input;
233 line-name = "RTC_EVENT#";
234 };
235 };
236
237 &gpio2 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_gpio2>;
240
241 gpio-line-names =
242 /* 00 */ "", "", "", "",
243 /* 04 */ "", "", "", "AFE_RESET#",
244 /* 08 */ "AFE_SYNC", "AFE_DRDY", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
245 /* 12 */ "", "", "", "",
246 /* 16 */ "X1_19", "X1_29", "X1_25", "X1_21",
247 /* 20 */ "X1_23", "X1_17", "", "",
248 /* 24 */ "AFE_INT#", "", "X1_15", "",
249 /* 28 */ "", "", "", "";
250 };
251
252 &gpio3 {
253 gpio-line-names =
254 /* 00 */ "SD2_CD#", "", "", "",
255 /* 04 */ "", "", "", "SD2_RST#",
256 /* 08 */ "", "", "", "",
257 /* 12 */ "", "", "", "",
258 /* 16 */ "", "", "", "",
259 /* 20 */ "", "", "", "",
260 /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
261 /* 28 */ "", "", "", "";
262
263 ethphy-eqos-irq-hog {
264 gpio-hog;
265 gpios = <26 GPIO_ACTIVE_LOW>;
266 input;
267 line-name = "ENET1_INT#";
268 };
269
270 ethphy-fec-irq-hog {
271 gpio-hog;
272 gpios = <27 GPIO_ACTIVE_LOW>;
273 input;
274 line-name = "ENET2_INT#";
275 };
276 };
277
278 &gpio4 {
279 gpio-line-names =
280 /* 00 */ "", "", "", "",
281 /* 04 */ "", "", "", "",
282 /* 08 */ "", "", "", "",
283 /* 12 */ "", "", "", "",
284 /* 16 */ "", "", "", "",
285 /* 20 */ "", "", "", "",
286 /* 24 */ "", "", "", "",
287 /* 28 */ "", "DP_INT", "", "";
288
289 dp-int-hog {
290 gpio-hog;
291 gpios = <29 GPIO_ACTIVE_LOW>;
292 input;
293 line-name = "DP_INT";
294 };
295 };
296
297 &lpi2c3 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 clock-frequency = <400000>;
301 pinctrl-names = "default", "sleep";
302 pinctrl-0 = <&pinctrl_lpi2c3>;
303 pinctrl-1 = <&pinctrl_lpi2c3>;
304 status = "okay";
305
306 temperature-sensor@1c {
307 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
308 reg = <0x1c>;
309 };
310
311 ptn5110: usb-typec@50 {
312 compatible = "nxp,ptn5110", "tcpci";
313 reg = <0x50>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_typec>;
316 interrupt-parent = <&gpio1>;
317 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
318
319 connector {
320 compatible = "usb-c-connector";
321 label = "X17";
322 power-role = "dual";
323 data-role = "dual";
324 try-power-role = "sink";
325 typec-power-opmode = "default";
326 pd-disable;
327 self-powered;
328
329 port {
330 typec_con_hs: endpoint {
331 remote-endpoint = <&typec_hs>;
332 };
333 };
334 };
335 };
336
337 eeprom2: eeprom@54 {
338 compatible = "nxp,se97b", "atmel,24c02";
339 reg = <0x54>;
340 pagesize = <16>;
341 vcc-supply = <®_3v3>;
342 };
343
344 expander0: gpio@70 {
345 compatible = "nxp,pca9538";
346 reg = <0x70>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_pexp_irq>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 interrupt-parent = <&gpio1>;
354 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
355 vcc-supply = <®_3v3>;
356 gpio-line-names = "3V8_EN", "",
357 "", "IOT_PWRKEY",
358 "IOT_RESET", "IOT_W_DISABLE",
359 "BUTTON_A#", "BUTTON_B#";
360
361 /*
362 * Controls the IOT W_DISABLE pin which is low active
363 * as disable signal but inverted as seen from the CPU.
364 * The output-low states, the signal is
365 * inactive, e.g. not disabled
366 */
367 iot_wdisable_hog: iot-wdisable-hog {
368 gpio-hog;
369 gpios = <5 GPIO_ACTIVE_HIGH>;
370 output-low;
371 line-name = "IOT_W_DISABLE";
372 };
373 };
374
375 expander1: gpio@71 {
376 compatible = "nxp,pca9538";
377 reg = <0x71>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 vcc-supply = <®_3v3>;
381 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
382 "USB_RESET#", "",
383 "WLAN_PD#", "WLAN_W_DISABLE#",
384 "WLAN_PERST#", "12V_EN";
385
386 /*
387 * Controls the WiFi card PD pin which is low active
388 * as power down signal. The output-low states, the signal
389 * is inactive, e.g. not power down
390 */
391 wlan-pd-hog {
392 gpio-hog;
393 gpios = <4 GPIO_ACTIVE_LOW>;
394 output-low;
395 line-name = "WLAN_PD#";
396 };
397
398 /*
399 * Controls the WiFi card disable pin which is low active
400 * as disable signal. The output-low states, the signal
401 * is inactive, e.g. not disabled
402 */
403 wlan-wdisable-hog {
404 gpio-hog;
405 gpios = <5 GPIO_ACTIVE_LOW>;
406 output-low;
407 line-name = "WLAN_W_DISABLE#";
408 };
409
410 /*
411 * Controls the WiFi card reset pin which is low active
412 * as reset signal. The output-low states, the signal
413 * is inactive, e.g. not in reset
414 */
415 wlan-perst-hog {
416 gpio-hog;
417 gpios = <6 GPIO_ACTIVE_LOW>;
418 output-low;
419 line-name = "WLAN_PERST#";
420 };
421 };
422
423 expander2: gpio@72 {
424 compatible = "nxp,pca9538";
425 reg = <0x72>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 vcc-supply = <®_3v3>;
429 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
430 "LCD_BLT_EN", "DP_EN",
431 "MIPI_CSI_EN", "MIPI_CSI_RST#",
432 "USER_LED1", "USER_LED2";
433 };
434 };
435
436 &lpi2c5 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clock-frequency = <400000>;
440 pinctrl-names = "default", "sleep";
441 pinctrl-0 = <&pinctrl_lpi2c5>;
442 pinctrl-1 = <&pinctrl_lpi2c5>;
443 status = "okay";
444
445 dp_bridge: dp-bridge@f {
446 compatible = "toshiba,tc9595", "toshiba,tc358767";
447 reg = <0x0f>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_tc9595>;
450 clock-names = "ref";
451 clocks = <&clk_dp>;
452 reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
453 interrupt-parent = <&gpio4>;
454 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
455 toshiba,hpd-pin = <0>;
456 status = "disabled";
457
458 ports {
459 #address-cells = <1>;
460 #size-cells = <0>;
461
462 port@0 {
463 reg = <0>;
464
465 dp_dsi_in: endpoint {
466 data-lanes = <1 2 3 4>;
467 };
468 };
469 };
470 };
471 };
472
473 &lpspi6 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>;
476 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
477 status = "okay";
478 };
479
480 &lpuart1 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_uart1>;
483 status = "okay";
484 };
485
486 &lpuart2 {
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart2>;
489 linux,rs485-enabled-at-boot-time;
490 status = "okay";
491 };
492
493 /* disabled per default, console for M33 */
494 &lpuart3 {
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart3>;
497 status = "disabled";
498 };
499
500 &lpuart6 {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_uart6>;
503 status = "okay";
504 };
505
506 &lpuart8 {
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_uart8>;
509 status = "okay";
510 };
511
512 &pcf85063 {
513 /* RTC_EVENT# from SoM is connected on mainboard */
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_pcf85063>;
516 interrupt-parent = <&gpio1>;
517 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
518 };
519
520 &se97_som {
521 /* TEMP_EVENT# from SoM is connected on mainboard */
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_temp_sensor_som>;
524 interrupt-parent = <&gpio1>;
525 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
526 };
527
528 &tpm5 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_tpm5>;
531 };
532
533 &usbotg1 {
534 dr_mode = "otg";
535 hnp-disable;
536 srp-disable;
537 adp-disable;
538 usb-role-switch;
539 disable-over-current;
540 samsung,picophy-pre-emp-curr-control = <3>;
541 samsung,picophy-dc-vol-level-adjust = <7>;
542 status = "okay";
543
544 port {
545 typec_hs: endpoint {
546 remote-endpoint = <&typec_con_hs>;
547 };
548 };
549 };
550
551 &usbotg2 {
552 dr_mode = "host";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 disable-over-current;
556 samsung,picophy-pre-emp-curr-control = <3>;
557 samsung,picophy-dc-vol-level-adjust = <7>;
558 status = "okay";
559
560 hub_2_0: usb-hub@1 {
561 compatible = "usb424,2517";
562 reg = <1>;
563 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
564 vdd-supply = <®_3v3>;
565 };
566 };
567
568 &usdhc2 {
569 pinctrl-names = "default", "state_100mhz", "state_200mhz";
570 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
571 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
572 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
573 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
574 vmmc-supply = <®_usdhc2_vmmc>;
575 bus-width = <4>;
576 no-sdio;
577 no-mmc;
578 disable-wp;
579 status = "okay";
580 };
581
582 &iomuxc {
583 pinctrl_afe: afegrp {
584 fsl,pins = <
585 /* FSEL_2 | DSE X4 */
586 MX93_PAD_GPIO_IO07__GPIO2_IO07 0x011e
587 /* PD | FSEL_2 | DSE X4 */
588 MX93_PAD_GPIO_IO08__GPIO2_IO08 0x051e
589 /* HYS | PD */
590 MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1400
591 /* HYS */
592 MX93_PAD_GPIO_IO24__GPIO2_IO24 0x1000
593 >;
594 };
595
596 pinctrl_eqos: eqosgrp {
597 fsl,pins = <
598 /* PD | FSEL_2 | DSE X4 */
599 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
600 /* SION | HYS | FSEL_2 | DSE X4 */
601 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
602 /* HYS | FSEL_0 | DSE no drive */
603 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
604 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
605 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000
606 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000
607 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000
608 /* HYS | PD | FSEL_0 | DSE no drive */
609 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400
610 /* PD | FSEL_2 | DSE X4 */
611 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
612 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
613 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
614 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
615 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
616 /* PD | FSEL_3 | DSE X3 */
617 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
618 >;
619 };
620
621 pinctrl_eqos_phy: eqosphygrp {
622 fsl,pins = <
623 /* HYS | FSEL_0 | DSE no drive */
624 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000
625 >;
626 };
627
628 pinctrl_fec: fecgrp {
629 fsl,pins = <
630 /* PD | FSEL_2 | DSE X4 */
631 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
632 /* SION | HYS | FSEL_2 | DSE X4 */
633 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
634 /* HYS | FSEL_0 | DSE no drive */
635 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
636 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000
637 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000
638 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000
639 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000
640 /* HYS | PD | FSEL_0 | DSE no drive */
641 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400
642 /* PD | FSEL_2 | DSE X4 */
643 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
644 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
645 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
646 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
647 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
648 /* PD | FSEL_3 | DSE X3 */
649 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
650 >;
651 };
652
653 pinctrl_fec_phy: fecphygrp {
654 fsl,pins = <
655 /* HYS | FSEL_0 | DSE no drive */
656 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000
657 >;
658 };
659
660 pinctrl_flexcan1: flexcan1grp {
661 fsl,pins = <
662 /* HYS | PU | FSEL_0 | DSE no drive */
663 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200
664 /* PU | FSEL_3 | DSE X4 */
665 MX93_PAD_PDM_CLK__CAN1_TX 0x039e
666 >;
667 };
668
669 pinctrl_flexcan2: flexcan2grp {
670 fsl,pins = <
671 /* HYS | PU | FSEL_0 | DSE no drive */
672 MX93_PAD_GPIO_IO27__CAN2_RX 0x1200
673 /* PU | FSEL_3 | DSE X4 */
674 MX93_PAD_GPIO_IO25__CAN2_TX 0x039e
675 >;
676 };
677
678 pinctrl_gpio2: gpio2grp {
679 fsl,pins = <
680 /* HYS | PD | FSEL_2 | DSE X4 */
681 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x151e
682 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x151e
683 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x151e
684 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x151e
685 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x151e
686 MX93_PAD_GPIO_IO21__GPIO2_IO21 0x151e
687 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x151e
688 >;
689 };
690
691 pinctrl_jtag: jtaggrp {
692 fsl,pins = <
693 MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e
694 MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200
695 MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e
696 MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200
697 >;
698 };
699
700 pinctrl_lpi2c3: lpi2c3grp {
701 fsl,pins = <
702 /* SION | HYS | OD | FSEL_3 | DSE X4 */
703 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e
704 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e
705 >;
706 };
707
708 pinctrl_lpi2c5: lpi2c5grp {
709 fsl,pins = <
710 /* SION | HYS | OD | FSEL_3 | DSE X4 */
711 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e
712 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e
713 >;
714 };
715
716 pinctrl_lpspi6: lpspi6grp {
717 fsl,pins = <
718 /* HYS | PD | FSEL_0 | DSE no drive */
719 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x1400
720 /* PD | FSEL_2 | DSE X4 */
721 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e
722 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x051e
723 >;
724 };
725
726 pinctrl_lpspi6_cs: lpspi6csgrp {
727 fsl,pins = <
728 /* FSEL_2 | DSE X4 */
729 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x011e
730 >;
731 };
732
733 pinctrl_mipi_csi: mipicsigrp {
734 fsl,pins = <
735 MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */
736 MX93_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */
737 MX93_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */
738 >;
739 };
740
741 pinctrl_pcf85063: pcf85063grp {
742 fsl,pins = <
743 /* HYS | FSEL_0 | No DSE */
744 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000
745 >;
746 };
747
748 pinctrl_pexp_irq: pexpirqgrp {
749 fsl,pins = <
750 /* HYS | FSEL_0 | No DSE */
751 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1000
752 >;
753 };
754
755 pinctrl_tc9595: tc9595-grp {
756 fsl,pins = <
757 /* HYS | PD | FSEL_0 | no DSE */
758 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400
759 >;
760 };
761
762 pinctrl_temp_sensor_som: tempsensorsomgrp {
763 fsl,pins = <
764 /* HYS | FSEL_0 | no DSE */
765 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000
766 >;
767 };
768
769 pinctrl_tpm5: tpm5grp {
770 fsl,pins = <
771 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
772 >;
773 };
774
775 pinctrl_typec: typecgrp {
776 fsl,pins = <
777 /* HYS | FSEL_0 | No DSE */
778 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1000
779 >;
780 };
781
782 pinctrl_uart1: uart1grp {
783 fsl,pins = <
784 /* HYS | FSEL_0 | No DSE */
785 MX93_PAD_UART1_RXD__LPUART1_RX 0x1000
786 /* FSEL_2 | DSE X4 */
787 MX93_PAD_UART1_TXD__LPUART1_TX 0x011e
788 >;
789 };
790
791 pinctrl_uart2: uart2grp {
792 fsl,pins = <
793 /* HYS | FSEL_0 | No DSE */
794 MX93_PAD_UART2_RXD__LPUART2_RX 0x1000
795 /* FSEL_2 | DSE X4 */
796 MX93_PAD_UART2_TXD__LPUART2_TX 0x011e
797 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e
798 >;
799 };
800
801 pinctrl_uart3: uart3grp {
802 fsl,pins = <
803 /* HYS | FSEL_0 | No DSE */
804 MX93_PAD_GPIO_IO15__LPUART3_RX 0x1000
805 /* FSEL_2 | DSE X4 */
806 MX93_PAD_GPIO_IO14__LPUART3_TX 0x011e
807 >;
808 };
809
810 pinctrl_uart6: uart6grp {
811 fsl,pins = <
812 /* HYS | FSEL_0 | No DSE */
813 MX93_PAD_GPIO_IO05__LPUART6_RX 0x1000
814 /* FSEL_2 | DSE X4 */
815 MX93_PAD_GPIO_IO04__LPUART6_TX 0x011e
816 >;
817 };
818
819 pinctrl_uart8: uart8grp {
820 fsl,pins = <
821 /* HYS | FSEL_0 | No DSE */
822 MX93_PAD_GPIO_IO13__LPUART8_RX 0x1000
823 /* FSEL_2 | DSE X4 */
824 MX93_PAD_GPIO_IO12__LPUART8_TX 0x011e
825 >;
826 };
827
828 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
829 fsl,pins = <
830 /* HYS | FSEL_0 | No DSE */
831 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000
832 >;
833 };
834
835 /* enable SION for data and cmd pad due to ERR052021 */
836 pinctrl_usdhc2_hs: usdhc2hsgrp {
837 fsl,pins = <
838 /* PD | FSEL_3 | DSE X5 */
839 MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be
840 /* HYS | PU | FSEL_3 | DSE X4 */
841 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
842 /* HYS | PU | FSEL_3 | DSE X3 */
843 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
844 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
845 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
846 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
847 /* FSEL_2 | DSE X3 */
848 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
849 >;
850 };
851
852 /* enable SION for data and cmd pad due to ERR052021 */
853 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
854 fsl,pins = <
855 /* PD | FSEL_3 | DSE X6 */
856 MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe
857 /* HYS | PU | FSEL_3 | DSE X4 */
858 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
859 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
860 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
861 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
862 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
863 /* FSEL_2 | DSE X3 */
864 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
865 >;
866 };
867 };
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