1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 */
7
8 #include "imx93.dtsi"
9
10 /{
11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
12 compatible = "tq,imx93-tqma9352", "fsl,imx93";
13
14 reserved-memory {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 ranges;
18
19 linux,cma {
20 compatible = "shared-dma-pool";
21 reusable;
22 alloc-ranges = <0 0x80000000 0 0x40000000>;
23 size = <0 0x10000000>;
24 linux,cma-default;
25 };
26 };
27
28 /* SD2 RST# via PMIC SW_EN */
29 reg_usdhc2_vmmc: regulator-usdhc2 {
30 compatible = "regulator-fixed";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
33 regulator-name = "VSD_3V3";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 vin-supply = <&buck4>;
37 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40 };
41
42 &adc1 {
43 vref-supply = <&buck5>;
44 };
45
46 &flexspi1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_flexspi1>;
49 status = "okay";
50
51 flash0: flash@0 {
52 compatible = "jedec,spi-nor";
53 reg = <0>;
54 /*
55 * no DQS, RXCLKSRC internal loop back, max 66 MHz
56 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST
57 * selected value together with root from
58 * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
59 * respect the maximum value.
60 */
61 spi-max-frequency = <62000000>;
62 spi-tx-bus-width = <4>;
63 spi-rx-bus-width = <4>;
64
65 partitions {
66 compatible = "fixed-partitions";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 };
70 };
71 };
72
73 &gpio1 {
74 pmic-irq-hog {
75 gpio-hog;
76 gpios = <3 GPIO_ACTIVE_LOW>;
77 input;
78 line-name = "PMIC_IRQ#";
79 };
80 };
81
82 &lpi2c1 {
83 clock-frequency = <400000>;
84 pinctrl-names = "default", "sleep";
85 pinctrl-0 = <&pinctrl_lpi2c1>;
86 pinctrl-1 = <&pinctrl_lpi2c1>;
87 status = "okay";
88
89 se97_som: temperature-sensor@1b {
90 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
91 reg = <0x1b>;
92 };
93
94 pca9451a: pmic@25 {
95 compatible = "nxp,pca9451a";
96 reg = <0x25>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_pca9451>;
99 interrupt-parent = <&gpio1>;
100 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
101
102 regulators {
103 /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
104 buck1: BUCK1 {
105 regulator-name = "BUCK1";
106 regulator-min-microvolt = <750000>;
107 regulator-max-microvolt = <900000>;
108 regulator-boot-on;
109 regulator-always-on;
110 regulator-ramp-delay = <3125>;
111 };
112
113 /* V_DDRQ - 1.1 LPDDR4 or 0.6 LPDDR4X */
114 buck2: BUCK2 {
115 regulator-name = "BUCK2";
116 regulator-min-microvolt = <600000>;
117 regulator-max-microvolt = <1100000>;
118 regulator-boot-on;
119 regulator-always-on;
120 regulator-ramp-delay = <3125>;
121 };
122
123 /* V_3V3 - EEPROM, RTC, ... */
124 buck4: BUCK4 {
125 regulator-name = "BUCK4";
126 regulator-min-microvolt = <3300000>;
127 regulator-max-microvolt = <3300000>;
128 regulator-boot-on;
129 regulator-always-on;
130 };
131
132 /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
133 buck5: BUCK5 {
134 regulator-name = "BUCK5";
135 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <1800000>;
137 regulator-boot-on;
138 regulator-always-on;
139 };
140
141 /* V_1V1 - RAM VDD2*/
142 buck6: BUCK6 {
143 regulator-name = "BUCK6";
144 regulator-min-microvolt = <1100000>;
145 regulator-max-microvolt = <1100000>;
146 regulator-boot-on;
147 regulator-always-on;
148 };
149
150 /* V_1V8_BBSM, fix 1.8 */
151 ldo1: LDO1 {
152 regulator-name = "LDO1";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 /* V_0V8_ANA */
160 ldo4: LDO4 {
161 regulator-name = "LDO4";
162 regulator-min-microvolt = <800000>;
163 regulator-max-microvolt = <800000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
169 ldo5: LDO5 {
170 regulator-name = "LDO5";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176 };
177 };
178
179 pcf85063: rtc@51 {
180 compatible = "nxp,pcf85063a";
181 reg = <0x51>;
182 quartz-load-femtofarads = <7000>;
183 };
184
185 eeprom0: eeprom@53 {
186 compatible = "nxp,se97b", "atmel,24c02";
187 reg = <0x53>;
188 pagesize = <16>;
189 read-only;
190 vcc-supply = <&buck4>;
191 };
192
193 eeprom1: eeprom@57 {
194 compatible = "atmel,24c64";
195 reg = <0x57>;
196 pagesize = <32>;
197 vcc-supply = <&buck4>;
198 };
199
200 /* protectable identification memory (part of M24C64-D @57) */
201 eeprom@5f {
202 compatible = "atmel,24c64d-wl";
203 reg = <0x5f>;
204 vcc-supply = <&buck4>;
205 };
206
207 imu@6a {
208 compatible = "st,ism330dhcx";
209 reg = <0x6a>;
210 vdd-supply = <&buck4>;
211 vddio-supply = <&buck4>;
212 };
213 };
214
215 &usdhc1 {
216 pinctrl-names = "default", "state_100mhz", "state_200mhz";
217 pinctrl-0 = <&pinctrl_usdhc1>;
218 pinctrl-1 = <&pinctrl_usdhc1>;
219 pinctrl-2 = <&pinctrl_usdhc1>;
220 vmmc-supply = <&buck4>;
221 vqmmc-supply = <&buck5>;
222 bus-width = <8>;
223 non-removable;
224 no-sdio;
225 no-sd;
226 status = "okay";
227 };
228
229 &wdog3 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_wdog>;
232 fsl,ext-reset-output;
233 status = "okay";
234 };
235
236 &iomuxc {
237 pinctrl_flexspi1: flexspi1grp {
238 fsl,pins = <
239 /* FSEL 3 | DSE X6 */
240 MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe
241 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe
242 /* HYS | PU | FSEL 3 | DSE X6 */
243 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x13fe
244 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x13fe
245 /* HYS | FSEL 3 | DSE X6 (external PU) */
246 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x11fe
247 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x11fe
248 >;
249 };
250
251 pinctrl_lpi2c1: lpi2c1grp {
252 fsl,pins = <
253 /* SION | OD | FSEL 3 | DSE X4 */
254 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e
255 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e
256 >;
257 };
258
259 pinctrl_pca9451: pca9451grp {
260 fsl,pins = <
261 /* HYS | PU */
262 MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1200
263 >;
264 };
265
266 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
267 fsl,pins = <
268 /* FSEL 2 | DSE X2 */
269 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106
270 >;
271 };
272
273 /* enable SION for data and cmd pad due to ERR052021 */
274 pinctrl_usdhc1: usdhc1grp {
275 fsl,pins = <
276 /* PD | FSEL 3 | DSE X5 */
277 MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
278 /* HYS | FSEL 0 | no drive */
279 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
280 /* HYS | FSEL 3 | X5 */
281 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
282 /* HYS | FSEL 3 | X4 */
283 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
284 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
285 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
286 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
287 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
288 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
289 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
290 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
291 >;
292 };
293
294 pinctrl_wdog: wdoggrp {
295 fsl,pins = <
296 /* PU | FSEL 1 | DSE X4 */
297 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
298 >;
299 };
300 };
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