1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
11
12 / {
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges;
21
22 service_reserved: svcbuffer@0 {
23 compatible = "shared-dma-pool";
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
26 no-map;
27 };
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 compatible = "arm,cortex-a53";
36 device_type = "cpu";
37 enable-method = "psci";
38 reg = <0x0>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "arm,cortex-a53";
43 device_type = "cpu";
44 enable-method = "psci";
45 reg = <0x1>;
46 };
47
48 cpu2: cpu@2 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 enable-method = "psci";
52 reg = <0x2>;
53 };
54
55 cpu3: cpu@3 {
56 compatible = "arm,cortex-a53";
57 device_type = "cpu";
58 enable-method = "psci";
59 reg = <0x3>;
60 };
61 };
62
63 firmware {
64 svc {
65 compatible = "intel,agilex-svc";
66 method = "smc";
67 memory-region = <&service_reserved>;
68
69 fpga_mgr: fpga-mgr {
70 compatible = "intel,agilex-soc-fpga-mgr";
71 };
72 };
73 };
74
75 fpga-region {
76 compatible = "fpga-region";
77 #address-cells = <0x2>;
78 #size-cells = <0x2>;
79 fpga-mgr = <&fpga_mgr>;
80 };
81
82 pmu {
83 compatible = "arm,cortex-a53-pmu";
84 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-affinity = <&cpu0>,
89 <&cpu1>,
90 <&cpu2>,
91 <&cpu3>;
92 interrupt-parent = <&intc>;
93 };
94
95 psci {
96 compatible = "arm,psci-0.2";
97 method = "smc";
98 };
99
100 intc: interrupt-controller@fffc1000 {
101 compatible = "arm,gic-400", "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x0 0xfffc1000 0x0 0x1000>,
105 <0x0 0xfffc2000 0x0 0x2000>,
106 <0x0 0xfffc4000 0x0 0x2000>,
107 <0x0 0xfffc6000 0x0 0x2000>;
108 };
109
110 clocks {
111 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 };
115
116 cb_intosc_ls_clk: cb-intosc-ls-clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 };
120
121 f2s_free_clk: f2s-free-clk {
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
124 };
125
126 osc1: osc1 {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 };
130
131 qspi_clk: qspi-clk {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <200000000>;
135 };
136 };
137
138 timer {
139 compatible = "arm,armv8-timer";
140 interrupt-parent = <&intc>;
141 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
142 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
145 };
146
147 usbphy0: usbphy {
148 #phy-cells = <0>;
149 compatible = "usb-nop-xceiv";
150 };
151
152 soc@0 {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "simple-bus";
156 device_type = "soc";
157 interrupt-parent = <&intc>;
158 ranges = <0 0 0 0xffffffff>;
159
160 clkmgr: clock-controller@ffd10000 {
161 compatible = "intel,agilex-clkmgr";
162 reg = <0xffd10000 0x1000>;
163 #clock-cells = <1>;
164 };
165
166 gmac0: ethernet@ff800000 {
167 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
168 reg = <0xff800000 0x2000>;
169 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "macirq";
171 mac-address = [00 00 00 00 00 00];
172 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
173 reset-names = "stmmaceth", "ahb";
174 tx-fifo-depth = <16384>;
175 rx-fifo-depth = <16384>;
176 snps,multicast-filter-bins = <256>;
177 iommus = <&smmu 1>;
178 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
179 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
180 clock-names = "stmmaceth", "ptp_ref";
181 status = "disabled";
182 };
183
184 gmac1: ethernet@ff802000 {
185 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
186 reg = <0xff802000 0x2000>;
187 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "macirq";
189 mac-address = [00 00 00 00 00 00];
190 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
191 reset-names = "stmmaceth", "ahb";
192 tx-fifo-depth = <16384>;
193 rx-fifo-depth = <16384>;
194 snps,multicast-filter-bins = <256>;
195 iommus = <&smmu 2>;
196 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
197 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
198 clock-names = "stmmaceth", "ptp_ref";
199 status = "disabled";
200 };
201
202 gmac2: ethernet@ff804000 {
203 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
204 reg = <0xff804000 0x2000>;
205 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-names = "macirq";
207 mac-address = [00 00 00 00 00 00];
208 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
209 reset-names = "stmmaceth", "ahb";
210 tx-fifo-depth = <16384>;
211 rx-fifo-depth = <16384>;
212 snps,multicast-filter-bins = <256>;
213 iommus = <&smmu 3>;
214 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
215 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
216 clock-names = "stmmaceth", "ptp_ref";
217 status = "disabled";
218 };
219
220 gpio0: gpio@ffc03200 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "snps,dw-apb-gpio";
224 reg = <0xffc03200 0x100>;
225 resets = <&rst GPIO0_RESET>;
226 status = "disabled";
227
228 porta: gpio-controller@0 {
229 compatible = "snps,dw-apb-gpio-port";
230 gpio-controller;
231 #gpio-cells = <2>;
232 snps,nr-gpios = <24>;
233 reg = <0>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
237 };
238 };
239
240 gpio1: gpio@ffc03300 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "snps,dw-apb-gpio";
244 reg = <0xffc03300 0x100>;
245 resets = <&rst GPIO1_RESET>;
246 status = "disabled";
247
248 portb: gpio-controller@0 {
249 compatible = "snps,dw-apb-gpio-port";
250 gpio-controller;
251 #gpio-cells = <2>;
252 snps,nr-gpios = <24>;
253 reg = <0>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
257 };
258 };
259
260 i2c0: i2c@ffc02800 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "snps,designware-i2c";
264 reg = <0xffc02800 0x100>;
265 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
266 resets = <&rst I2C0_RESET>;
267 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
268 status = "disabled";
269 };
270
271 i2c1: i2c@ffc02900 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "snps,designware-i2c";
275 reg = <0xffc02900 0x100>;
276 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
277 resets = <&rst I2C1_RESET>;
278 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
279 status = "disabled";
280 };
281
282 i2c2: i2c@ffc02a00 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "snps,designware-i2c";
286 reg = <0xffc02a00 0x100>;
287 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
288 resets = <&rst I2C2_RESET>;
289 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
290 status = "disabled";
291 };
292
293 i2c3: i2c@ffc02b00 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "snps,designware-i2c";
297 reg = <0xffc02b00 0x100>;
298 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
299 resets = <&rst I2C3_RESET>;
300 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
301 status = "disabled";
302 };
303
304 i2c4: i2c@ffc02c00 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "snps,designware-i2c";
308 reg = <0xffc02c00 0x100>;
309 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
310 resets = <&rst I2C4_RESET>;
311 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
312 status = "disabled";
313 };
314
315 mmc: mmc@ff808000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "altr,socfpga-dw-mshc";
319 reg = <0xff808000 0x1000>;
320 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
321 fifo-depth = <0x400>;
322 resets = <&rst SDMMC_RESET>;
323 reset-names = "reset";
324 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
325 <&clkmgr AGILEX_SDMMC_CLK>;
326 clock-names = "biu", "ciu";
327 iommus = <&smmu 5>;
328 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
329 status = "disabled";
330 };
331
332 nand: nand-controller@ffb90000 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 compatible = "altr,socfpga-denali-nand";
336 reg = <0xffb90000 0x10000>,
337 <0xffb80000 0x1000>;
338 reg-names = "nand_data", "denali_reg";
339 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clkmgr AGILEX_NAND_CLK>,
341 <&clkmgr AGILEX_NAND_X_CLK>,
342 <&clkmgr AGILEX_NAND_ECC_CLK>;
343 clock-names = "nand", "nand_x", "ecc";
344 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
345 status = "disabled";
346 };
347
348 ocram: sram@ffe00000 {
349 compatible = "mmio-sram";
350 reg = <0xffe00000 0x40000>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges = <0 0xffe00000 0x40000>;
354 };
355
356 pdma: dma-controller@ffda0000 {
357 compatible = "arm,pl330", "arm,primecell";
358 reg = <0xffda0000 0x1000>;
359 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
368 #dma-cells = <1>;
369 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
370 reset-names = "dma", "dma-ocp";
371 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
372 clock-names = "apb_pclk";
373 };
374
375 pinctrl0: pinctrl@ffd13000 {
376 compatible = "pinctrl-single";
377 #pinctrl-cells = <1>;
378 reg = <0xffd13000 0xa0>;
379 pinctrl-single,register-width = <32>;
380 pinctrl-single,function-mask = <0x0000000f>;
381 };
382
383 pinctrl1: pinctrl@ffd13100 {
384 compatible = "pinctrl-single";
385 #pinctrl-cells = <1>;
386 reg = <0xffd13100 0x20>;
387 pinctrl-single,register-width = <32>;
388 };
389
390 rst: rstmgr@ffd11000 {
391 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
392 reg = <0xffd11000 0x100>;
393 #reset-cells = <1>;
394 };
395
396 smmu: iommu@fa000000 {
397 compatible = "arm,mmu-500", "arm,smmu-v2";
398 reg = <0xfa000000 0x40000>;
399 #global-interrupts = <2>;
400 #iommu-cells = <1>;
401 interrupt-parent = <&intc>;
402 /* Global Secure Fault */
403 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
404 /* Global Non-secure Fault */
405 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
406 /* Non-secure Context Interrupts (32) */
407 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
439 stream-match-mask = <0x7ff0>;
440 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
441 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
442 <&clkmgr AGILEX_L4_MAIN_CLK>;
443 status = "disabled";
444 };
445
446 spi0: spi@ffda4000 {
447 compatible = "snps,dw-apb-ssi";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 reg = <0xffda4000 0x1000>;
451 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
452 resets = <&rst SPIM0_RESET>;
453 reset-names = "spi";
454 reg-io-width = <4>;
455 num-cs = <4>;
456 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
457 status = "disabled";
458 };
459
460 spi1: spi@ffda5000 {
461 compatible = "snps,dw-apb-ssi";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 reg = <0xffda5000 0x1000>;
465 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
466 resets = <&rst SPIM1_RESET>;
467 reset-names = "spi";
468 reg-io-width = <4>;
469 num-cs = <4>;
470 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
471 status = "disabled";
472 };
473
474 sysmgr: sysmgr@ffd12000 {
475 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
476 reg = <0xffd12000 0x500>;
477 };
478
479 timer0: timer0@ffc03000 {
480 compatible = "snps,dw-apb-timer";
481 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
482 reg = <0xffc03000 0x100>;
483 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
484 clock-names = "timer";
485 };
486
487 timer1: timer1@ffc03100 {
488 compatible = "snps,dw-apb-timer";
489 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
490 reg = <0xffc03100 0x100>;
491 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
492 clock-names = "timer";
493 };
494
495 timer2: timer2@ffd00000 {
496 compatible = "snps,dw-apb-timer";
497 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
498 reg = <0xffd00000 0x100>;
499 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
500 clock-names = "timer";
501 };
502
503 timer3: timer3@ffd00100 {
504 compatible = "snps,dw-apb-timer";
505 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
506 reg = <0xffd00100 0x100>;
507 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
508 clock-names = "timer";
509 };
510
511 uart0: serial@ffc02000 {
512 compatible = "snps,dw-apb-uart";
513 reg = <0xffc02000 0x100>;
514 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
515 reg-shift = <2>;
516 reg-io-width = <4>;
517 resets = <&rst UART0_RESET>;
518 status = "disabled";
519 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
520 };
521
522 uart1: serial@ffc02100 {
523 compatible = "snps,dw-apb-uart";
524 reg = <0xffc02100 0x100>;
525 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
526 reg-shift = <2>;
527 reg-io-width = <4>;
528 resets = <&rst UART1_RESET>;
529 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
530 status = "disabled";
531 };
532
533 usb0: usb@ffb00000 {
534 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
535 reg = <0xffb00000 0x40000>;
536 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
537 phys = <&usbphy0>;
538 phy-names = "usb2-phy";
539 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
540 reset-names = "dwc2", "dwc2-ecc";
541 clocks = <&clkmgr AGILEX_USB_CLK>;
542 clock-names = "otg";
543 iommus = <&smmu 6>;
544 status = "disabled";
545 };
546
547 usb1: usb@ffb40000 {
548 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
549 reg = <0xffb40000 0x40000>;
550 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
551 phys = <&usbphy0>;
552 phy-names = "usb2-phy";
553 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
554 reset-names = "dwc2", "dwc2-ecc";
555 iommus = <&smmu 7>;
556 clocks = <&clkmgr AGILEX_USB_CLK>;
557 status = "disabled";
558 };
559
560 watchdog0: watchdog@ffd00200 {
561 compatible = "snps,dw-wdt";
562 reg = <0xffd00200 0x100>;
563 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
564 resets = <&rst WATCHDOG0_RESET>;
565 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
566 status = "disabled";
567 };
568
569 watchdog1: watchdog@ffd00300 {
570 compatible = "snps,dw-wdt";
571 reg = <0xffd00300 0x100>;
572 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
573 resets = <&rst WATCHDOG1_RESET>;
574 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
575 status = "disabled";
576 };
577
578 watchdog2: watchdog@ffd00400 {
579 compatible = "snps,dw-wdt";
580 reg = <0xffd00400 0x100>;
581 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
582 resets = <&rst WATCHDOG2_RESET>;
583 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
584 status = "disabled";
585 };
586
587 watchdog3: watchdog@ffd00500 {
588 compatible = "snps,dw-wdt";
589 reg = <0xffd00500 0x100>;
590 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
591 resets = <&rst WATCHDOG3_RESET>;
592 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
593 status = "disabled";
594 };
595
596 sdr: sdr@f8011100 {
597 compatible = "altr,sdr-ctl", "syscon";
598 reg = <0xf8011100 0xc0>;
599 };
600
601 eccmgr {
602 compatible = "altr,socfpga-s10-ecc-manager",
603 "altr,socfpga-a10-ecc-manager";
604 altr,sysmgr-syscon = <&sysmgr>;
605 #address-cells = <1>;
606 #size-cells = <1>;
607 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
610 ranges;
611
612 sdramedac {
613 compatible = "altr,sdram-edac-s10";
614 altr,sdr-syscon = <&sdr>;
615 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
616 };
617
618 ocram-ecc@ff8cc000 {
619 compatible = "altr,socfpga-s10-ocram-ecc",
620 "altr,socfpga-a10-ocram-ecc";
621 reg = <0xff8cc000 0x100>;
622 altr,ecc-parent = <&ocram>;
623 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
624 };
625
626 usb0-ecc@ff8c4000 {
627 compatible = "altr,socfpga-s10-usb-ecc",
628 "altr,socfpga-usb-ecc";
629 reg = <0xff8c4000 0x100>;
630 altr,ecc-parent = <&usb0>;
631 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
632 };
633
634 emac0-rx-ecc@ff8c0000 {
635 compatible = "altr,socfpga-s10-eth-mac-ecc",
636 "altr,socfpga-eth-mac-ecc";
637 reg = <0xff8c0000 0x100>;
638 altr,ecc-parent = <&gmac0>;
639 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
640 };
641
642 emac0-tx-ecc@ff8c0400 {
643 compatible = "altr,socfpga-s10-eth-mac-ecc",
644 "altr,socfpga-eth-mac-ecc";
645 reg = <0xff8c0400 0x100>;
646 altr,ecc-parent = <&gmac0>;
647 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
648 };
649
650 sdmmca-ecc@ff8c8c00 {
651 compatible = "altr,socfpga-s10-sdmmc-ecc",
652 "altr,socfpga-sdmmc-ecc";
653 reg = <0xff8c8c00 0x100>;
654 altr,ecc-parent = <&mmc>;
655 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
656 <15 IRQ_TYPE_LEVEL_HIGH>;
657 };
658 };
659
660 qspi: spi@ff8d2000 {
661 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 reg = <0xff8d2000 0x100>,
665 <0xff900000 0x100000>;
666 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
667 cdns,fifo-depth = <128>;
668 cdns,fifo-width = <4>;
669 cdns,trigger-address = <0x00000000>;
670 clocks = <&qspi_clk>;
671
672 status = "disabled";
673 };
674 };
675 };
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