1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP806.
6 */
7
8 #include "armada-ap806.dtsi"
9
10 / {
11 model = "Marvell Armada AP806 Dual";
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a72";
21 reg = <0x000>;
22 enable-method = "psci";
23 #cooling-cells = <2>;
24 clocks = <&cpu_clk 0>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
27 i-cache-sets = <256>;
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 next-level-cache = <&l2>;
32 };
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a72";
36 reg = <0x001>;
37 enable-method = "psci";
38 #cooling-cells = <2>;
39 clocks = <&cpu_clk 0>;
40 i-cache-size = <0xc000>;
41 i-cache-line-size = <64>;
42 i-cache-sets = <256>;
43 d-cache-size = <0x8000>;
44 d-cache-line-size = <64>;
45 d-cache-sets = <256>;
46 next-level-cache = <&l2>;
47 };
48
49 l2: l2-cache {
50 compatible = "cache";
51 cache-size = <0x80000>;
52 cache-line-size = <64>;
53 cache-sets = <512>;
54 cache-level = <2>;
55 cache-unified;
56 };
57 };
58
59 thermal-zones {
60 /delete-node/ ap-thermal-cpu2;
61 /delete-node/ ap-thermal-cpu3;
62 };
63 };
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