1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada CP11x.
6 */
7
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
10
11 #include "armada-common.dtsi"
12
13 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
14
15 / {
16 /*
17 * The contents of the node are defined below, in order to
18 * save one indentation level
19 */
20 CP11X_NAME: CP11X_NAME { };
21
22 /*
23 * CPs only have one sensor in the thermal IC.
24 *
25 * The cooling maps are empty as there are no cooling devices.
26 */
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
31
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
33
34 trips {
35 CP11X_LABEL(crit): crit {
36 temperature = <100000>; /* mC degrees */
37 hysteresis = <2000>; /* mC degrees */
38 type = "critical";
39 };
40 };
41
42 cooling-maps { };
43 };
44 };
45 };
46
47 &CP11X_NAME {
48 #address-cells = <2>;
49 #size-cells = <2>;
50 compatible = "simple-bus";
51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
52 ranges;
53
54 config-space@CP11X_BASE {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
59
60 CP11X_LABEL(ethernet): ethernet@0 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "marvell,armada-7k-pp22";
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
65 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
66 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
67 <&CP11X_LABEL(clk) 1 18>;
68 clock-names = "pp_clk", "gop_clk",
69 "mg_clk", "mg_core_clk", "axi_clk";
70 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
71 status = "disabled";
72 dma-coherent;
73
74 CP11X_LABEL(eth0): ethernet-port@0 {
75 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
76 <43 IRQ_TYPE_LEVEL_HIGH>,
77 <47 IRQ_TYPE_LEVEL_HIGH>,
78 <51 IRQ_TYPE_LEVEL_HIGH>,
79 <55 IRQ_TYPE_LEVEL_HIGH>,
80 <59 IRQ_TYPE_LEVEL_HIGH>,
81 <63 IRQ_TYPE_LEVEL_HIGH>,
82 <67 IRQ_TYPE_LEVEL_HIGH>,
83 <71 IRQ_TYPE_LEVEL_HIGH>,
84 <129 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-names = "hif0", "hif1", "hif2",
86 "hif3", "hif4", "hif5", "hif6", "hif7",
87 "hif8", "link";
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
90 gop-port-id = <0>;
91 status = "disabled";
92 };
93
94 CP11X_LABEL(eth1): ethernet-port@1 {
95 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
96 <44 IRQ_TYPE_LEVEL_HIGH>,
97 <48 IRQ_TYPE_LEVEL_HIGH>,
98 <52 IRQ_TYPE_LEVEL_HIGH>,
99 <56 IRQ_TYPE_LEVEL_HIGH>,
100 <60 IRQ_TYPE_LEVEL_HIGH>,
101 <64 IRQ_TYPE_LEVEL_HIGH>,
102 <68 IRQ_TYPE_LEVEL_HIGH>,
103 <72 IRQ_TYPE_LEVEL_HIGH>,
104 <128 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-names = "hif0", "hif1", "hif2",
106 "hif3", "hif4", "hif5", "hif6", "hif7",
107 "hif8", "link";
108 reg = <1>;
109 port-id = <1>; /* For backward compatibility. */
110 gop-port-id = <2>;
111 status = "disabled";
112 };
113
114 CP11X_LABEL(eth2): ethernet-port@2 {
115 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
116 <45 IRQ_TYPE_LEVEL_HIGH>,
117 <49 IRQ_TYPE_LEVEL_HIGH>,
118 <53 IRQ_TYPE_LEVEL_HIGH>,
119 <57 IRQ_TYPE_LEVEL_HIGH>,
120 <61 IRQ_TYPE_LEVEL_HIGH>,
121 <65 IRQ_TYPE_LEVEL_HIGH>,
122 <69 IRQ_TYPE_LEVEL_HIGH>,
123 <73 IRQ_TYPE_LEVEL_HIGH>,
124 <127 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-names = "hif0", "hif1", "hif2",
126 "hif3", "hif4", "hif5", "hif6", "hif7",
127 "hif8", "link";
128 reg = <2>;
129 port-id = <2>; /* For backward compatibility. */
130 gop-port-id = <3>;
131 status = "disabled";
132 };
133 };
134
135 CP11X_LABEL(comphy): phy@120000 {
136 compatible = "marvell,comphy-cp110";
137 reg = <0x120000 0x6000>;
138 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
139 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
140 <&CP11X_LABEL(clk) 1 18>;
141 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 CP11X_LABEL(comphy0): phy@0 {
146 reg = <0>;
147 #phy-cells = <1>;
148 };
149
150 CP11X_LABEL(comphy1): phy@1 {
151 reg = <1>;
152 #phy-cells = <1>;
153 };
154
155 CP11X_LABEL(comphy2): phy@2 {
156 reg = <2>;
157 #phy-cells = <1>;
158 };
159
160 CP11X_LABEL(comphy3): phy@3 {
161 reg = <3>;
162 #phy-cells = <1>;
163 };
164
165 CP11X_LABEL(comphy4): phy@4 {
166 reg = <4>;
167 #phy-cells = <1>;
168 };
169
170 CP11X_LABEL(comphy5): phy@5 {
171 reg = <5>;
172 #phy-cells = <1>;
173 };
174 };
175
176 CP11X_LABEL(mdio): mdio@12a200 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "marvell,orion-mdio";
180 reg = <0x12a200 0x10>;
181 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
182 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
183 status = "disabled";
184 };
185
186 CP11X_LABEL(xmdio): mdio@12a600 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "marvell,xmdio";
190 reg = <0x12a600 0x10>;
191 clocks = <&CP11X_LABEL(clk) 1 5>,
192 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
193 status = "disabled";
194 };
195
196 CP11X_LABEL(icu): interrupt-controller@1e0000 {
197 compatible = "marvell,cp110-icu";
198 reg = <0x1e0000 0x440>;
199 #address-cells = <1>;
200 #size-cells = <1>;
201
202 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
203 compatible = "marvell,cp110-icu-nsr";
204 reg = <0x10 0x20>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 msi-parent = <&gicp>;
208 };
209
210 CP11X_LABEL(icu_sei): interrupt-controller@50 {
211 compatible = "marvell,cp110-icu-sei";
212 reg = <0x50 0x10>;
213 #interrupt-cells = <2>;
214 interrupt-controller;
215 msi-parent = <&sei>;
216 };
217 };
218
219 CP11X_LABEL(rtc): rtc@284000 {
220 compatible = "marvell,armada-8k-rtc";
221 reg = <0x284000 0x20>, <0x284080 0x24>;
222 reg-names = "rtc", "rtc-soc";
223 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 CP11X_LABEL(syscon0): system-controller@440000 {
227 compatible = "syscon", "simple-mfd";
228 reg = <0x440000 0x2000>;
229
230 CP11X_LABEL(clk): clock {
231 compatible = "marvell,cp110-clock";
232 #clock-cells = <2>;
233 };
234
235 CP11X_LABEL(gpio1): gpio@100 {
236 compatible = "marvell,armada-8k-gpio";
237 offset = <0x100>;
238 ngpios = <32>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
242 marvell,pwm-offset = <0x1f0>;
243 #pwm-cells = <2>;
244 interrupt-controller;
245 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
246 <85 IRQ_TYPE_LEVEL_HIGH>,
247 <84 IRQ_TYPE_LEVEL_HIGH>,
248 <83 IRQ_TYPE_LEVEL_HIGH>;
249 #interrupt-cells = <2>;
250 clock-names = "core", "axi";
251 clocks = <&CP11X_LABEL(clk) 1 21>,
252 <&CP11X_LABEL(clk) 1 17>;
253 status = "disabled";
254 };
255
256 CP11X_LABEL(gpio2): gpio@140 {
257 compatible = "marvell,armada-8k-gpio";
258 offset = <0x140>;
259 ngpios = <31>;
260 gpio-controller;
261 #gpio-cells = <2>;
262 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
263 marvell,pwm-offset = <0x1f0>;
264 #pwm-cells = <2>;
265 interrupt-controller;
266 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
267 <81 IRQ_TYPE_LEVEL_HIGH>,
268 <80 IRQ_TYPE_LEVEL_HIGH>,
269 <79 IRQ_TYPE_LEVEL_HIGH>;
270 #interrupt-cells = <2>;
271 clock-names = "core", "axi";
272 clocks = <&CP11X_LABEL(clk) 1 21>,
273 <&CP11X_LABEL(clk) 1 17>;
274 status = "disabled";
275 };
276 };
277
278 CP11X_LABEL(syscon1): system-controller@400000 {
279 compatible = "syscon", "simple-mfd";
280 reg = <0x400000 0x1000>;
281 #address-cells = <1>;
282 #size-cells = <1>;
283
284 CP11X_LABEL(thermal): thermal-sensor@70 {
285 compatible = "marvell,armada-cp110-thermal";
286 reg = <0x70 0x10>;
287 interrupts-extended =
288 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
289 #thermal-sensor-cells = <1>;
290 };
291 };
292
293 CP11X_LABEL(utmi): utmi@580000 {
294 compatible = "marvell,cp110-utmi-phy";
295 reg = <0x580000 0x2000>;
296 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300
301 CP11X_LABEL(utmi0): usb-phy@0 {
302 reg = <0>;
303 #phy-cells = <0>;
304 };
305
306 CP11X_LABEL(utmi1): usb-phy@1 {
307 reg = <1>;
308 #phy-cells = <0>;
309 };
310 };
311
312 CP11X_LABEL(usb3_0): usb@500000 {
313 compatible = "marvell,armada-8k-xhci",
314 "generic-xhci";
315 reg = <0x500000 0x4000>;
316 dma-coherent;
317 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
318 clock-names = "core", "reg";
319 clocks = <&CP11X_LABEL(clk) 1 22>,
320 <&CP11X_LABEL(clk) 1 16>;
321 status = "disabled";
322 };
323
324 CP11X_LABEL(usb3_1): usb@510000 {
325 compatible = "marvell,armada-8k-xhci",
326 "generic-xhci";
327 reg = <0x510000 0x4000>;
328 dma-coherent;
329 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
330 clock-names = "core", "reg";
331 clocks = <&CP11X_LABEL(clk) 1 23>,
332 <&CP11X_LABEL(clk) 1 16>;
333 status = "disabled";
334 };
335
336 CP11X_LABEL(sata0): sata@540000 {
337 compatible = "marvell,armada-8k-ahci",
338 "generic-ahci";
339 reg = <0x540000 0x30000>;
340 dma-coherent;
341 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&CP11X_LABEL(clk) 1 15>,
343 <&CP11X_LABEL(clk) 1 16>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 status = "disabled";
347
348 sata-port@0 {
349 reg = <0>;
350 };
351
352 sata-port@1 {
353 reg = <1>;
354 };
355 };
356
357 CP11X_LABEL(xor0): xor@6a0000 {
358 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
359 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
360 dma-coherent;
361 msi-parent = <&gic_v2m0>;
362 clock-names = "core", "reg";
363 clocks = <&CP11X_LABEL(clk) 1 8>,
364 <&CP11X_LABEL(clk) 1 14>;
365 };
366
367 CP11X_LABEL(xor1): xor@6c0000 {
368 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
369 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
370 dma-coherent;
371 msi-parent = <&gic_v2m0>;
372 clock-names = "core", "reg";
373 clocks = <&CP11X_LABEL(clk) 1 7>,
374 <&CP11X_LABEL(clk) 1 14>;
375 };
376
377 CP11X_LABEL(spi0): spi@700600 {
378 compatible = "marvell,armada-380-spi";
379 reg = <0x700600 0x50>;
380 #address-cells = <0x1>;
381 #size-cells = <0x0>;
382 clock-names = "core", "axi";
383 clocks = <&CP11X_LABEL(clk) 1 21>,
384 <&CP11X_LABEL(clk) 1 17>;
385 status = "disabled";
386 };
387
388 CP11X_LABEL(spi1): spi@700680 {
389 compatible = "marvell,armada-380-spi";
390 reg = <0x700680 0x50>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393 clock-names = "core", "axi";
394 clocks = <&CP11X_LABEL(clk) 1 21>,
395 <&CP11X_LABEL(clk) 1 17>;
396 status = "disabled";
397 };
398
399 CP11X_LABEL(i2c0): i2c@701000 {
400 compatible = "marvell,mv78230-i2c";
401 reg = <0x701000 0x20>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
405 clock-names = "core", "reg";
406 clocks = <&CP11X_LABEL(clk) 1 21>,
407 <&CP11X_LABEL(clk) 1 17>;
408 status = "disabled";
409 };
410
411 CP11X_LABEL(i2c1): i2c@701100 {
412 compatible = "marvell,mv78230-i2c";
413 reg = <0x701100 0x20>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
417 clock-names = "core", "reg";
418 clocks = <&CP11X_LABEL(clk) 1 21>,
419 <&CP11X_LABEL(clk) 1 17>;
420 status = "disabled";
421 };
422
423 CP11X_LABEL(uart0): serial@702000 {
424 compatible = "snps,dw-apb-uart";
425 reg = <0x702000 0x100>;
426 reg-shift = <2>;
427 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
428 reg-io-width = <1>;
429 clock-names = "baudclk", "apb_pclk";
430 clocks = <&CP11X_LABEL(clk) 1 21>,
431 <&CP11X_LABEL(clk) 1 17>;
432 status = "disabled";
433 };
434
435 CP11X_LABEL(uart1): serial@702100 {
436 compatible = "snps,dw-apb-uart";
437 reg = <0x702100 0x100>;
438 reg-shift = <2>;
439 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
440 reg-io-width = <1>;
441 clock-names = "baudclk", "apb_pclk";
442 clocks = <&CP11X_LABEL(clk) 1 21>,
443 <&CP11X_LABEL(clk) 1 17>;
444 status = "disabled";
445 };
446
447 CP11X_LABEL(uart2): serial@702200 {
448 compatible = "snps,dw-apb-uart";
449 reg = <0x702200 0x100>;
450 reg-shift = <2>;
451 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
452 reg-io-width = <1>;
453 clock-names = "baudclk", "apb_pclk";
454 clocks = <&CP11X_LABEL(clk) 1 21>,
455 <&CP11X_LABEL(clk) 1 17>;
456 status = "disabled";
457 };
458
459 CP11X_LABEL(uart3): serial@702300 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0x702300 0x100>;
462 reg-shift = <2>;
463 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
464 reg-io-width = <1>;
465 clock-names = "baudclk", "apb_pclk";
466 clocks = <&CP11X_LABEL(clk) 1 21>,
467 <&CP11X_LABEL(clk) 1 17>;
468 status = "disabled";
469 };
470
471 CP11X_LABEL(nand_controller): nand-controller@720000 {
472 /*
473 * Due to the limitation of the pins available
474 * this controller is only usable on the CPM
475 * for A7K and on the CPS for A8K.
476 */
477 compatible = "marvell,armada-8k-nand-controller",
478 "marvell,armada370-nand-controller";
479 reg = <0x720000 0x54>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
483 clock-names = "core", "reg";
484 clocks = <&CP11X_LABEL(clk) 1 2>,
485 <&CP11X_LABEL(clk) 1 17>;
486 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
487 status = "disabled";
488 };
489
490 CP11X_LABEL(trng): trng@760000 {
491 compatible = "marvell,armada-8k-rng",
492 "inside-secure,safexcel-eip76";
493 reg = <0x760000 0x7d>;
494 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
495 clock-names = "core", "reg";
496 clocks = <&CP11X_LABEL(clk) 1 25>,
497 <&CP11X_LABEL(clk) 1 17>;
498 status = "okay";
499 };
500
501 CP11X_LABEL(sdhci0): mmc@780000 {
502 compatible = "marvell,armada-cp110-sdhci";
503 reg = <0x780000 0x300>;
504 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
505 clock-names = "core", "axi";
506 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
507 dma-coherent;
508 status = "disabled";
509 };
510
511 CP11X_LABEL(crypto): crypto@800000 {
512 compatible = "inside-secure,safexcel-eip197b";
513 reg = <0x800000 0x200000>;
514 interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
515 <89 IRQ_TYPE_LEVEL_HIGH>,
516 <90 IRQ_TYPE_LEVEL_HIGH>,
517 <91 IRQ_TYPE_LEVEL_HIGH>,
518 <92 IRQ_TYPE_LEVEL_HIGH>,
519 <87 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-names = "ring0", "ring1", "ring2", "ring3",
521 "eip", "mem";
522 clock-names = "core", "reg";
523 clocks = <&CP11X_LABEL(clk) 1 26>,
524 <&CP11X_LABEL(clk) 1 17>;
525 dma-coherent;
526 };
527 };
528
529 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
530 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
531 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
532 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
533 reg-names = "ctrl", "config";
534 #address-cells = <3>;
535 #size-cells = <2>;
536 #interrupt-cells = <1>;
537 device_type = "pci";
538 dma-coherent;
539 msi-parent = <&gic_v2m0>;
540
541 bus-range = <0 0xff>;
542 /* non-prefetchable memory */
543 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
544 interrupt-map-mask = <0 0 0 0>;
545 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
546 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
547 num-lanes = <1>;
548 clock-names = "core", "reg";
549 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
550 status = "disabled";
551 };
552
553 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
554 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
555 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
556 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
557 reg-names = "ctrl", "config";
558 #address-cells = <3>;
559 #size-cells = <2>;
560 #interrupt-cells = <1>;
561 device_type = "pci";
562 dma-coherent;
563 msi-parent = <&gic_v2m0>;
564
565 bus-range = <0 0xff>;
566 /* non-prefetchable memory */
567 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
568 interrupt-map-mask = <0 0 0 0>;
569 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
570 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
571
572 num-lanes = <1>;
573 clock-names = "core", "reg";
574 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
575 status = "disabled";
576 };
577
578 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
579 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
580 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
581 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
582 reg-names = "ctrl", "config";
583 #address-cells = <3>;
584 #size-cells = <2>;
585 #interrupt-cells = <1>;
586 device_type = "pci";
587 dma-coherent;
588 msi-parent = <&gic_v2m0>;
589
590 bus-range = <0 0xff>;
591 /* non-prefetchable memory */
592 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
595 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
596
597 num-lanes = <1>;
598 clock-names = "core", "reg";
599 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
600 status = "disabled";
601 };
602 };
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